參數資料
| 型號： | TVP5150APBSRG4 |
| 廠商： | Texas Instruments |
| 文件頁數： | 14/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DECODER 8BIT 32TQFP |
| 產品培訓模塊： | Data Converter Basics |
| 標準包裝： | 1,000 |
| 類型： | 視頻解碼器 |
| 應用： | 移動電話，PDA，播放器 |
| 電壓 - 電源，模擬： | 1.8V |
| 電壓 - 電源，數字： | 1.8V，3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應商設備封裝： | 32-TQFP（5x5） |
| 包裝： | 帶卷 (TR) |
| 配用： | TVP5150AEVM-ND - TVP5150AEVM 296-23058-ND - EVAL MODULE FOR DM642 TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁
211
2.15.2.2 Read Phase 2
Step 7
0
I2C Start (master)
S
Step 8
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
0
X
1
Step 9
9
I2C Acknowledge (slave)
A
Step 10
7
6
5
4
3
2
1
0
I2C Read data (slave)
Data
Step 11
9
I2C Not acknowledge (master)
A
Step 12
0
I2C Stop (master)
P
Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
2.15.2.3 I2C Timing Requirements
The TVP5150A decoder requires delays in the I2C accesses to accommodate its internal processor’s timing. In
accordance with I2C specifications, the TVP5150A decoder holds the I2C clock line (SCL) low to indicate the wait
period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the
maximum delays must always be inserted where required. These delays are of variable length; maximum delays are
indicated in the following diagram:
Normal register writing address 00h8Fh (addresses 90hFFh do not require delays)
Start
Slave address
(B8h)
Ack
Subaddress
Ack
Data
(XXh)
Ack
Wait 64
s
Stop
2.16 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive the PLL.
This may be input to the TVP5150A decoder on terminal 5 (XTAL1), or a crystal of 14.31818-MHz fundamental
resonant frequency may be connected across terminals 5 and 6 (XTAL2). Figure 25 shows the reference clock
configurations. For the example crystal circuit shown (a parallel-resonant crystal with 14.31818-MHz fundamental
frequency), the external capacitors must have the following relationship:
CL1 = CL2 = 2CL CSTRAY,
where CSTRAY is the terminal capacitance with respect to ground. Figure 25 shows the reference clock
configurations.
TVP5150A
5
XTAL1
14.31818-MHz
Crystal
6
XTAL2
TVP5150A
5
XTAL1
6
XTAL2
CL1
CL2
14.31818-MHz
TTL Clock
Figure 25. Reference Clock Configurations
相關PDF資料 |
PDF描述 |
|---|---|
| TVP5154AIPNP | IC VIDEO DECODER 4CH 128-HTQFP |
| TW2804-FE | IC NTSC/PAL VIDEO DECOD 128PQF |
| TW2809-BC1-GR | IC INTERFACE |
| TW2815-TA1-GR | IC A/V CODEC/DECOD 4CH 100TQFP |
| TW2816-TA1-GR | IC A/V CODEC/DECOD 4CH 100TQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TVP5150PBS | 功能描述:編碼器、解碼器、復用器和解復用器 VERY LOW POWER VIDEO DECODER RoHS:否 制造商:Micrel 產品:Multiplexers 邏輯系列:CMOS 位數: 線路數量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| TVP5150PBS | 制造商:Texas Instruments 功能描述:IC DECODER VIDEO SMD |
| TVP5150PBSG4 | 功能描述:視頻 IC VERY LOW POWER VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5150PBSR | 功能描述:視頻 IC Very Low Power Video Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5150PBSRG4 | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。