參數(shù)資料
型號(hào)： TVP5150AM1ZQCR
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PBGA48
封裝： GREEN, PLASTIC, BGA-48
文件頁數(shù)： 27/88頁
文件大?。?/td> 997K
代理商： TVP5150AM1ZQCR
www.ti.com
SLES209D – NOVEMBER 2007 – REVISED SEPTEMBER 2010
HSYNC, VSYNC/PALI, active video indicator (AVID), and FID/GLCO output enables
0 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high-impedance (default).
1 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are active.
Note: This control bit has no effect on the FID/GLCO output when it is programmed to output the
GLCO signal (see bit 3 of address 0Fh). When the GLCO signal is selected, the FID/GLCO output is
always active.
Vertical blanking on/off
0 = Vertical blanking (VBLK) off (default)
1 = Vertical blanking (VBLK) on
Clock output enable
0 = SCLK output is high impedance
1 = SCLK output is enabled (default)
Note: To achieve lowest power consumption, outputs placed in the high-impedance state should not be
left floating. A 10-k
Ω pulldown resistor is recommended if not driven externally.
Note: When enabling the outputs, ensure the clock output is not accidently disabled.
Table 3-13. Digital Output Control(1)
REGISTER 03h, BIT 3
REGISTER C2h, BIT 2
YCbCr OUTPUT
NOTES
(TVPOE)
(VDPOE)
0
X
High impedance
After both YCbCr output enable bits are programmed
X
0
High impedance
After both YCbCr output enable bits are programmed
1
Active
After both YCbCr output enable bits are programmed
(1)
VDPOE default is 1, and TVPOE default is 0.
Copyright 2007–2010, Texas Instruments Incorporated
Functional Description
33
Product Folder Link(s): TVP5150AM1
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