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SLES141G
– JULY 2005 – REVISED APRIL 2011
List of Figures
1-1
Functional Block Diagram
.......................................................................................................
131-2
Terminal Assignments Diagram
................................................................................................
132-1
Analog Processors and A/D Converters
......................................................................................
162-2
Digital Video Processing Block Diagram
......................................................................................
182-3
Composite and S-Video Processor
............................................................................................
192-8
Luminance Edge-Enhancer Peaking Block Diagram
........................................................................
222-9
Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling
............................................................
222-10
Y Component Gain, Offset, Limit
...............................................................................................
232-11
CbCr Component Gain, Offset, Limit
..........................................................................................
232-12
Reference Clock Configurations
................................................................................................
242-13
RTC Timing
.......................................................................................................................
242-14
Vertical Synchronization Signals for 525-Line System
......................................................................
282-15
Vertical Synchronization Signals for 625-Line System
......................................................................
292-16
Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode
..................................................................
302-17
Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode
..................................................................
312-18
VSYNC Position With Respect to HSYNC
....................................................................................
312-19
VBUS Access
.....................................................................................................................
342-20
Reset Timing
......................................................................................................................
372-21
Teletext Filter Function
..........................................................................................................
763-1
Clocks, Video Data, and Sync Timing
.........................................................................................
953-2
I
2C Host Port Timing
.............................................................................................................
955-1
Example Application Circuit
...................................................................................................
1004
List of Figures
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2005–2011, Texas Instruments Incorporated