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參數(shù)資料
| 型號： | TVP5041PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 80/106頁 |
| 文件大小： | 501K |
| 代理商： | TVP5041PFP |
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2.13.26 Chrominance Control 2
VIP address
11Bh
PHI address
1Bh
I2C address
1Bh
7
6
5
4
3
2
1
0
Reserved
Chrominance filter select
Chrominance output bandwidth (MHz):
NTSC CCIR601
NTSC Square Pixel
PAL CCIR601
PAL Square Pixel
00 =
1.2129
1.1026
1.2129
1.3252
01 =
0.8701
0.7910
0.8701
0.9507
10 =
0.7383
0.6712
0.7383
0.8066
11 =
0.5010
0.4554
0.5010
0.5474
Refer to Figures 2–6, 2-7, 2-8 and 2-9 for the frequency responses of the filters. The control 00 is default mode.
2.13.27 Interrupt Reset Register B
VIP address
11Ch
PHI address
1Ch
I2C address
1Ch
7
6
5
4
3
2
1
0
Software
init reset
Macrovision detect
changed reset
TVP command
ready reset
Field rate
changed reset
Line alternation
changed reset
Color lock
changed reset
H/V lock
changed reset
TV/VCR
changed reset
Software Init
0 = No effect on interrupt register B (default)
1 = Reset software init bit
Macrovision Detect Changed Reset
0 = No effect on interrupt register B (default)
1 = Reset Macrovision detect changed bit
TVP Command Ready Reset
0 = No effect on interrupt register B (default)
1 = Reset TVP command ready bit
Field Rate Changed Reset
0 = No effect on interrupt register B (default)
1 = Reset field rate changed bit
Line Alternation Changed Reset
0 = No effect on interrupt register B (default)
1 = Reset line alternation changed bit
Color Lock Changed Reset
0 = No effect on interrupt register B (default)
1 = Reset color lock changed bit
H/V Lock Changed Reset
0 = No effect on interrupt register B (default)
1 = Reset H/V lock changed bit
TV/VCR Changed Reset
0 = No effect on interrupt register B (default)
1 = Reset TV/VCR changed bit
The interrupt reset register B is used by the external processor to reset the interrupt status bits in the interrupt register
B. Bits loaded with a 1 allows the corresponding interrupt status bit to reset to 0. Bits loaded with a 0 have no effect
on the interrupt status bits.
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