參數(shù)資料
型號: TVP5031CPFP
廠商: Texas Instruments, Inc.
英文描述: Color Decoder Circuit
中文描述: 彩色解碼器電路
文件頁數(shù): 15/85頁
文件大?。?/td> 378K
代理商: TVP5031CPFP
1–7
1.6
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
Sync Signals (Continued)
NO.
PALI
32
I/O
PAL line indicator or horizontal lock indicator.
For PAL line indicator, a logic 1 indicates a noninverted line, and a logic 0 indicates an inverted line. For
horizontal lock indicator, a logic 1 indicates the internal horizontal PLL is in a locked state.
This terminal is an input terminal during reset and is used in conjunction with GLCO and FID to select the
mode of the host interface. During reset, this terminal can be pulled up to set a 1, or pulled down to set a 0.
VSYN
29
O
Vertical sync signal
1.7
Strapping Terminals Description
All of the following terminals have reset strapping options. The states of these terminals are sampled during reset
to configure TVP5031 for various modes of operation. These terminals are temporarily turned into inputs with weak
internal pulldowns (~40 k
resistor) during reset and return to their normal operation after reset. Each of the following
terminals can be pulled up with a 10-K
resistor to set a 1 to the corresponding bit or be left undriven during reset,
relying on the internal pulldown resistor to pull the terminal low to set a 0 to the corresponding bit.
TERMINAL
DESCRIPTION
NAME
AVID
NO.
28
Y, U/V output enable (bit 4) and HSYN, VSYN, AVID, FID, and PALI output enable (bit 3) of miscellaneous
control ( Register 03)
PREF
26
Clock enable bit (bit 0) of miscellaneous control ( Register 03)
FID
33
Host interface mode (see Table 2-2).
PALI
32
Host interface mode (see Table 2-2).
GLCO
31
Host interface mode (see Table 2-2).
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