參數(shù)資料
型號: TVP5031
廠商: Texas Instruments, Inc.
英文描述: NTSC/PAL VIDEO DECODER
中文描述: NTSC / PAL視頻解碼器
文件頁數(shù): 42/85頁
文件大?。?/td> 378K
代理商: TVP5031
2–26
2.6.4
Parallel Host Interface C
The terminal descriptions are defined in Table 2–6.
Table 2–6. Parallel Host Interface C Terminal Description
TYPE
I
Address bus from host
I/O
Bidirectional data bus
I
Chip select, active low
I
Data strobe, active low
I
Read, active high
Write, active low
O
Ready, active high
O
Interrupt request,
Open drain by default, active low, pullup resistor required
Can be configured, subaddress C2, as a conventional CMOS buffer, active high, no pullup required.
TERMINAL
A[1:0]
D[7:0]
VC3
VC2
VC1
SIGNAL
HA[1:0]
HD[7:0]
CS
DS
RD/WR
DESCRIPTION
VC0
INTREQ
RDY
Parallel host interface C timing is shown in Figure 2–29. The cycle is initiated by the host when VC2-DS transitions
low. The TVP5031 responds by pulling VC0-RDY low. The TVP5031 will then set VC0-RDY to high impedance, a
pullup resistor is required, to indicate the data was received or that the requested data is present on the bus. The host
then completes the cycle by pulling VC2-DS high.
A[0:1]
D[7:0]
WRITE
VC1 (R/W)
VC2 (DS)
VC0
(DTACK)
D[7:0]
READ
Write Data
t1
t7
t2
t3
t8
t9
t6
t2
t5
t4
VC3 (CS)
Read Data
Figure 2–29. Parallel Host Interface C Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
t1
t2
t3
t5
t6
t8
t9
A[1:0],D[0:7],VC1 setup until VC2 low
Delay VC0 LOW after VC2 low
A[1:0], D[0:7],VC1 hold after VC0 low
Delay VC0 high after VC2 high
Delay VC2 low(next cycle) after VC0 high
(Read cycle) D[7:0] setup until VC0 low
(Read cycle) D[7:0] hold after VC2 high
5
0
5
0
5
10
0
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