- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385951 > TVP3703-135 (Texas Instruments, Inc.) Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器) PDF資料下載
參數(shù)資料
| 型號： | TVP3703-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（雙鎖相環(huán)，先進(jìn)的視頻接口調(diào)色器） |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 427K |
| 代理商： | TVP3703-135 |
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
primary and secondary pixel mode combinations (continued)
Table 7. Primary and Secondary Pixel Mode Combinations
PRIMARY
MODE
SECONDARY MODE
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
00h
X
X
X
X
01h
X
X
X
X
02h
X
X
X
X
03h
X
X
X
X
04h
X
X
X
X
05h
X
06h
X
X
X
X
07h
X
X
X
X
08h
X
X
X
X
09h
X
NOTE 2: Pixel switching can only be performed when the PCLK to dot clock ratios for the
primary and secondary modes are the same.
programming of pixel modes using the PLL
The TVP3703 uses an internal PLL to generate the internal dot clock. This PLL automatically adjusts the PCLK
to dot clock ratio based on the multiplexing mode selected. Therefore no further programming is necessary.
pixel resolution and blanking periods in mode 09h
In mode 09h (packed 24-bit), latching 16 bits of data from 3 PCLK cycles generates a group of 2 pixels. This
means that the horizontal screen resolution must be an even number of pixels, and the number of PCLK cycles
during active display must be a multiple of 3.
Due to the internal phase relationships between PCLK and the pixel clock generated by the internal PLL, the
horizontal and vertical blanking period must also be an integral multiple of 3 PCLK cycles. This must be satisfied
so that the first pixel of each line always appears at the same point horizontally on the screen, from line to line
and from frame to frame.
Therefore mode 09h requires the following relationships must be satisfied:
Horizontally:
The total horizontal duration must be an integral multiple of 3 PCLKs.
i.e.,HTOT
3
integer, where HTOT
total horizontal duration in standard VGA registers.
Vertically:
The total vertical duration must be an integral multiple of 3 PCLKs.
i.e.,VTOT
3
HTOT
integer, where VTOT
total vertical duration in standard VGA registers.
In all standard VGA systems, if the horizontal requirement is met, the vertical requirement is also met.
VGA standard controllers normally satisfy the requirements described in this section because the horizontal
blanking period is specified in character widths (8 pixels wide), vertical blanking in terms of scan lines, and
resolution in even pixels.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3703FN | VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
| TVP5020TQFP | NTSC/PAL VIDEO DECODER |
| TVP5031 | NTSC/PAL VIDEO DECODER |
| TVP5031TQFP | NTSC/PAL VIDEO DECODER |
| TVP5031CPFP | Color Decoder Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3703-135CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3703FN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
| TVP4020AGFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP4020AGFN-8 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP5010 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL Video Decoder |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。