參數(shù)資料
型號: TVP3026-135APCE
廠商: Texas Instruments, Inc.
英文描述: Video Interface Palette
中文描述: 視頻接口面板
文件頁數(shù): 69/107頁
文件大?。?/td> 513K
代理商: TVP3026-135APCE
A–1
Appendix A
Frequency Synthesis PLL Register Settings
Table A–1 provides a listing of all possible frequency settings that may be used by the pixel clock PLL for
frequency synthesis using the common 14.31818 MHz crystal. The same register settings may be used for
the MCLK PLL provided that the MCLK maximum frequency of 100 MHz is not exceeded. The constraints
used to generate the table include limits for the VCO frequency and limits for the N-register value.
PLL Architecture
Reference Frequency (MHz)
Minimum VCO Frequency (MHz)
Maximum VCO Frequency (MHz)
Minimum N-Register Value (dec)
Maximum N-Register Value (dec)
— TVP3026
— 14.318180
— 110.000000
— 250.000000
— 40
— 62
Table A–1. PLL Register Settings for 14.31818 MHz Reference
OUTPUT
VCO
NREG
MREG
PREG
14.32
114.55
FE
3E
B3
14.89
119.13
E8
27
B3
14.91
119.32
E9
28
B3
14.94
119.53
EA
29
B3
14.97
119.75
EB
2A
B3
15.00
120.00
EC
2B
B3
15.03
120.27
ED
2C
B3
15.07
120.57
EE
2D
B3
15.11
120.91
EF
2E
B3
15.16
121.28
F0
2F
B3
15.21
121.70
F1
30
B3
15.27
122.18
F2
31
B3
15.34
122.73
F3
32
B3
15.42
123.36
F4
33
B3
15.46
123.71
E8
26
B3
15.51
124.09
F5
34
B3
15.56
124.51
EA
28
B3
15.62
124.96
F6
35
B3
15.68
125.45
EC
2A
B3
15.75
126.00
F7
36
B3
15.83
126.60
EE
2C
B3
15.91
127.27
F8
37
B3
16.00
128.02
F0
2E
B3
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TVP3026-135BMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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