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參數(shù)資料
| 型號： | TVP3010C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁數(shù)： | 17/90頁 |
| 文件大小： | 491K |
| 代理商： | TVP3010C |
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2–1
2 Detailed Description
The TVP3010C and TVP3010M VIPs are identical in their operation. Both the TVP3010C and TVP3010M
are 32-bit devices; both devices are terminal compatible with the TLC34076 and each device offers
advanced features. To facilitate the enhanced functionality, some terminals have dual functions. The
dual-function terminals are controlled by the configuration register discussed in subsection 2.16.1. At reset,
all pins default to the TLC34076 terminal functions.
2.1
The microprocessor unit (MPU) interface is controlled using read and write strobes (RD, WR), three
register-select terminals [RS(0–2)], and the 8/6-select terminal. The 8/6 pin selects between an 8- or
6-bit-wide data path to the color-palette RAM and is provided in order to maintain compatibility with the
IMSG176. Since the 8/6 [OVS] pin is a dual-function pin, 2 bits are provided in the configuration register to
control this function. Configuration-register bit 1 determines whether the 8/6 [OVS] pin operates as 8/6 or
OVS. If configuration register bit 1 is cleared to 0 (default), then 8/6 operation is controlled by the pin. With
8/6 held low, data on the lowest 6 bits of the data bus are internally shifted up by 2 bits to occupy the upper
6 bits at the output multiplexer and the bottom 2 bits are then cleared to 0. This operation is carried out in
order to utilize the maximum range of the DACs.
MPU Interface
The direct register map is shown in Table 2–1. Extended registers can be accessed through the index
register. The index register map is shown in Table 2–2. In general, the index register must first be loaded
with the target address value. Successive reads or writes from and to the data register then access the target
location. The MPU interface operates asynchronously, with data transfers being synchronized by internal
logic.
NOTE:
RS3 is a do not care for register addressing but is used as the PSEL input (see
Section 2.6).
Table 2–1. Direct Register Map
RS2
RS1
RS0
REGISTER ADDRESSED BY MPU
R/W
DEFAULT (HEX)
0
0
0
Palette Address Register – Write Mode
R/W
XX
0
0
1
Color Palette Holding Register
R/W
XX
0
1
0
Pixel Read Mask
R/W
FF
0
1
1
Palette Address Register – Read Mode
R/W
XX
1
0
0
Reserved
XX
1
0
1
Reserved
XX
1
1
0
Index Register
R/W
XX
1
1
1
Data Register
R/W
XX
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3010M | Video Interface Palette |
| TVP3020-175 | Video Interface PALETTE(視頻接口調(diào)色器) |
| TVP3020-135 | Video Interface PALETTE(視頻接口調(diào)色器) |
| TVP3025-135 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3025-175 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3010M | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-135MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-135PCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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