參數(shù)資料
型號: TVP3010-135
廠商: Texas Instruments, Inc.
英文描述: Hardware Cursor, GAMMA Correction VIP(135MHz,高/寬光標,伽馬校正,視頻接口調(diào)色板)
中文描述: 硬件光標,伽瑪校正貴賓(135MHz,高/寬光標,伽馬校正,視頻接口調(diào)色板)
文件頁數(shù): 11/100頁
文件大?。?/td> 571K
代理商: TVP3010-135
1–5
1.4
Ordering Information
TVP3010
– XXX
XX
Pixel Clock Frequency Indicator
MUST CONTAIN THREE CHARACTERS:
–85: 85-MHz pixel clock
–110: 110-MHz pixel clock
–135: 135-MHz pixel clock
–170: 170-MHz pixel clock
Package
MUST CONTAIN TWO LETTERS:
FN:
square plastic J-leaded chip carrier (formed leads)
1.5
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AVDD
CLK0
NO.
55, 57
Analog power. All AVDD terminals must be connected.
Dot clock 0 input. CLK0 can be selected to drive the dot clock at
frequencies up to 140 MHz. When VGA mode is active, the default clock
source is CLK0. The maximum frequency in VGA mode is 85 MHz.
77
I
(TTL
compatible)
CLK1, CLK2
75, 76
I
(TTL/ECL
compatible)
Dual-mode dot clock input. These inputs are essentially ECL-
compatible inputs, but two TTL clocks may be used on the CLK1 and
CLK2 if so selected in the input clock select register. These inputs may
be selected as the dot clock up to the device limit while in the ECL mode
or up to 140 MHz in the TTL mode.
CLK3[RCLK]
74
I/O
Dot clock 3 TTL input or reference clock output. When configured as
CLK3, this terminal is similar to CLK0 and can be selected to drive the
dot clock at frequencies up to 140 MHz. When configured as RCLK, this
terminal outputs the reference clock signal, which is similar to the SCLK
signal but not gated off during blank. This signal can be used for
pixel-port timing reference or other system synchronization. The
terminal defaults to CLK3 after reset.
CLK4[LCLK]
73
I
Dot clock 4 TTL input or pixel-port latch clock. This terminal can be
configured to drive dot clock frequencies up to 140 MHz, or it can be
configured as a latch clock input to latch pixel-port input data. This
terminal defaults to CLK4 after reset, and LCLK is internally connected
to RCLK to latch pixel-port data.
COMP
52
I
Compensation. COMP provides compensation for the internal
reference amplifier. A 0.1-
μ
F ceramic capacitor is required between this
terminal and AVDD. The COMP capacitor must be as close to the device
as possible to avoid noise pick up.
DVDD
D(0–7)
45, 81
Digital power. All DVDD terminals must be connected.
MPU interface data bus. These terminals are used to transfer data in
and out of the register map and palette/overlay RAM.
36–43
I/O
(TTL
compatible)
FS ADJUST
51
I
Full-scale adjustment. A resistor connected between this terminal and
ground controls the full-scale range of the DACs.
NOTE: All unused inputs should be tied to a logic level and not be allowed to float.
相關(guān)PDF資料
PDF描述
TVP3010-170 Hardware Cursor, GAMMA Correction VIP(170MHz,高/寬光標,伽馬校正,視頻接口調(diào)色板)
TVP3010-85 Hardware Cursor, GAMMA Correction VIP(85MHz,高/寬光標,伽馬校正,視頻接口調(diào)色板)
TVP3010C Video Interface Palette
TVP3010M Video Interface Palette
TVP3020-175 Video Interface PALETTE(視頻接口調(diào)色器)
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