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參數(shù)資料
| 型號： | TUA6020 |
| 廠商： | SIEMENS AG |
| 英文描述： | 2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier(兩波段電視調(diào)諧器（帶振蕩器、IF放大器）) |
| 中文描述： | 2波段電視調(diào)諧器混頻器振蕩器與均衡的中頻放大器（兩波段電視調(diào)諧器（帶振蕩器中頻放大器）鎖相環(huán)） |
| 文件頁數(shù)： | 17/38頁 |
| 文件大?。?/td> | 464K |
| 代理商： | TUA6020 |
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Functional Description
3 - 9
TUA6020
preliminary
Wireless Components
Confidential
Specification, March 2000
The software-switched ports PLOW, PMID and PHIGH are general-purpose
open-collector outputs. The test bit T1 = 1, switches the test signals fref
(i.e.fXTAL / 64) and fdiv (divided input signal) to PLOW and PMID respectively.
The lock detector resets the lock flag FL if the width of the charge pump current
pulses is wider than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL
= 1, the maximum deviation of the input frequency from the programmed fre-
quency is given by
α
f =
=
I
P
Γ
(K
VCO
/ f
XTAL
)
Γ=
(C1+C2) / (C1
Γ
C2)
where I
P
is the charge pump current, K
VCO
the VCO gain, f
XTAL
the crystal oscil-
lator frequency and C1, C2 the capacitances in the loop filter (
see Figure 4-1 Eval-
uation Board on page 2
). As the charge pump pulses at i.e. 62.5 kHz (= f
ref
), it
takes a maximum of 16
=←
s for FL to be reset after the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than
250 ns for eight consecutive f
ref
periods. Therefore it takes between 128 and
144
=←
s for FL to be set after the loop regains lock.
3.4.3
I
2
C-Bus Interface
Data is exchanged between the processor and the PLL via the I
2
C bus. The
clock is generated by the processor (input SCL), while pin SDA functions as an
input or output depending on the direction of the data (open collector, external
pull-up resistor). Both inputs have hysteresis and a low-pass characteristic,
which enhance the noise immunity of the I
2
C bus.
The data from the processor pass through an I
2
C bus controller. Depending on
their function the data are subsequently stored in registers. If the bus is free,
both lines will be in the marking state (SDA, SCL are HIGH). Each telegram
begins with the start condition and ends with the stop condition. Start condition:
SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH
while SCL remains HIGH. All further information transfer takes place during
SCL = LOW, and the data is forwarded to the control logic on the positive clock
edge.
The table
”
Bit Allocation
”
(
see Table 5-4 Bit Allocation Read / Write on page 10
)
should be referred to the following description. All telegrams are transmitted
byte-by-byte, followed by a ninth clock pulse, during which the control logic
returns the SDA line to LOW (acknowledge condition). The first byte is com-
prised of seven address bits. These are used by the processor to select the PLL
from several peripheral components (chip select). The LSB bit (R/W) deter-
mines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte.
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