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參數(shù)資料
| 型號： | tua 6010xS |
| 廠商： | SIEMENS AG |
| 英文描述： | TV Mixer-Oscillator-PLL(電視混頻器-振蕩器-鎖相環(huán)電路) |
| 中文描述： | 電視攪拌機(jī)振蕩器鎖相環(huán)（電視混頻器-振蕩器-鎖相環(huán)電路） |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 508K |
| 代理商： | TUA 6010XS |
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Functional Description
3 - 9
TUA 6010XS
preliminary
Wireless Components
Specification, August 1999
The software-switched ports P0, P1, P2 are general-purpose open-collector
outputs. The test bit T1 = 1, switches the test signals f
ref
(4 MHz / 64) and C
y
(divided input signal) to P0 and P1 respectively. P0, P1, P2 are bidirectional.
The lock detector resets the lock flag FL when the width of the charge pump cur-
rent pulses is greater than the period of the crystal oscillator (i.e. 250 ns).
Hence, when FL = 1, the maximum deviation of the input frequency from the
programmed frequency is given by
f =
±
I
P
(K
VCO
/ f
Q
) (C
1
+C
2
) / (C
1
C
2
)
where I
P
is the charge pump current, K
VCO
the VCO gain, f
Q
the crystal oscilla-
tor frequency and C
1
, C
2
the capacitances in the loop filter (see application cir-
cuit). As the charge pump pulses at 62.5 kHz (= f
ref
), it takes a maximum of
16
μ
s for FL to be reset after the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than
250 ns for eight consecutive f
ref
periods. Therefore it takes between 128 and
144
μ
s for FL to be set after the loop regains lock.
3.4.3
I
2
C-Bus Interface
Data is exchanged between the processor and the PLL via the I
2
C bus. The
clock is generated by the processor (input SCL), while pin SDA functions as an
input or output depending on the direction of the data (open collector, external
pull-up resistor). Both inputs have hysteresis and a low-pass characteristic,
which enhance the noise immunity of the I
2
C bus.
The data from the processor pass through an I
2
C bus controller. Depending on
their function the data are subsequently stored in registers. If the bus is free,
both lines will be in the marking state (SDA, SCL are HIGH). Each telegram
begins with the start condition and ends with the stop condition. Start condition:
SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH
while SCL remains HIGH. All further information transfer takes place during
SCL = LOW, and the data is forwarded to the control logic on the positive clock
edge.
The table 1 ”bit allocation” should be referred to the following description. All
telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during
which the control logic returns the SDA line to LOW (acknowledge condition).
The first byte is comprised of seven address bits. These are used by the pro-
cessor to select the PLL from several peripheral components (chip select). The
LSB bit (R/W) determines whether data are written into (R/W = 0) or read from
(R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte.
If the address byte indicates a READ operation, the PLL generates an acknowl-
edge and then shifts out the status byte onto the SDA line. If the processor gen-
erates an acknowledge, a further status byte is output; otherwise the data line
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