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參數(shù)資料
| 型號(hào)： | tua 4401k |
| 廠商： | SIEMENS AG |
| 英文描述： | FM Car Radio IC with PLL(FM車載電臺(tái)芯片(帶鎖相環(huán))) |
| 中文描述： | 汽車調(diào)頻收音機(jī)芯片（調(diào)頻車載電臺(tái)芯片（帶鎖相環(huán)）與鎖相環(huán)） |
| 文件頁數(shù)： | 41/41頁 |
| 文件大?。?/td> | 990K |
| 代理商： | TUA 4401K |
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Reference
5 - 14
TUA 4401K
Wireless Components
Specification, 17.02.00
2)
C
b
= capacitance of one bus line in pF.
Note that the maximum t
F
for the SDA and SCL bus lines quoted at 300ns is
longer than the specified maximum t
OF
for the output stages (250ns).This
allows series protection resistors to be connected between the SDA / SCL pins
and the SDA /SCL bus lines without exceeding the maximum specified t
F
.
Table 5-4
Parameter
Symbol
min
max
Unit
LOW level input voltage (SDA, SCL)
V
IL
-0.5
0.90
V
HIGH level input voltage (SDA, SCL)
V
IH
2.10
5.50
V
Pulse width of spikes which must be suppressed by the input fil-
ter
t
SP
0
50
ns
LOW level output voltage 3mA sink current (SDA)
V
OL
0
0.40
V
Output fall time from V
IHmin
to V
ILmax
with a bus capacitance
from 10pF to 400pFwith up to 3mA
t
OF
20+0.1C
b2)
250
ns
SCL clock frequency
f
SCL
0
400
kHz
Bus free time between a STOP and START condition
t
BUF
1.3
μs
Hold time (repeated) START condition. After this period, the first
clock pulse is generated.
t
HO.STA
0.6
μs
LOW period of the SCL clock
t
LOW
1.3
μs
HIGH period of the SCL clock
t
HIGH
0.6
μs
Set-up time for a repeated START condition
t
SU.STA
0.6
μs
Data hold time
t
HD.DAT
0
ns
Data set -up time
t
SU.DAT
100
ns
Rise, fall time of both SDA and SCL signals
t
R
, t
F
20+0.1C
b2)
300
ns
Set-up time for STOP condition
t
SU.STO
0.6
μs
Capacitive load for each bus line
C
b
400
pF
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