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參數資料
| 型號： | TSPC860SRMZPU40D4 |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 40 MHz, RISC PROCESSOR, PBGA357 |
| 封裝： | PLASTIC, BGA-357 |
| 文件頁數： | 21/90頁 |
| 文件大?。?/td> | 2351K |
| 代理商： | TSPC860SRMZPU40D4 |
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28
TSPC860
2129A–HIREL–08/02
JTAG and Debug Ports
TCK/DSCK or ALE_B/DSCK/AT1 (depending on the configuration of the DSCK func-
tion) should be connected to ground through a pull-down resistor to disable Debug
Mode as a default. When required, a debug mode controller tool externally drives this
signal high actively to put the TSPC860 into debug mode.
Two pins need special attention, depending on the version of TSPC860 used.
For TSPC860 rev B and later, TDI/DSDI should be pulled up to V
CC to keep it from
oscillating when unused.
For TSPC860 rev A.3 and earlier, TCK/DSCK should be connected to ground if it is
configured for its DSCK function, as stated above. However, for these versions of
the TSPC860, the pull-down resistor must be strong (for example, 1 k
to overcome
the internal pull-up resistor.
To allow application of any version of processor, perform both of the above actions.
Unused Inputs
In general, pull-up resistors should be used on any unused inputs to keep them from
oscillating. For example, if PCMCIA is not used, the PCMCIA input pins (WAIT_A,
WAIT_B, IP_A[0-8], IP_B[0-8]) should have external pull-up resistors. However, unused
pins of port A, B, C, or D can be configured as outputs, and, if they are configured as
outputs they do not require external terminations.
Unused Outputs
Unused outputs can be left unterminated.
Signal States During
Hardware Reset
During hardware reset (HRESET or PORESET), the signals of the TSPC860 behave as
follows:
The bus signals are high-impedance.
The port I/O signals are configured as inputs, and are therefore high-impedance.
The memory controller signals are driven to their inactive state.
However, some signal functions are determined by the reset configuration. When
HRESET is asserted, these signals immediately begin functioning as determined by the
reset configuration and are either high-impedance or are drive to their inactive state
accordingly. The behavior of these signals is shown in Table 12.
Table 3. Signal States during Hardware Reset
Signal
Behavior
BDIP/GPL_B5
BDIP: high impedance
GPL_B5: high
RSV/IRQ2
RSV: high
IRQ2: high impedance
KR/RETRY/IRQ4/SPKROUT
KR/RETRY/IRQ4: high impedance
SPKROUT: low
FRZ/IRQ6
FRZ: low
IRQ6: high impedance
ALE_B/DSCK/AT1
ALE_B: low
DSCK/AT1: high impedance
IP_B[0-1]/IWP[0-1]/VFLS[0-1]
IP_B[0-1]: high impedance
IWP[0-1]: high
VFLS[0-1]: low
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