
29
TSPC750A/740A
2128A–HIREL–01/02
Figure17providestheJTAGclockinputtimingdiagram.
Figure17.
JTAGClockInputTimingDiagram
Figure18providestheTRST
timingdiagram.
Figure18.
TRSTTimingDiagram
Figure19providestheboundary-scantimingdiagram.
Figure19.
Boundary-ScanTimingDiagram
TCK
2
2
1
VM
VM
VM
3
3
VM = Midpoint Voltage
5
TRST
6
7
8
9
8
TCK
DATA INPUTS
DATA OUTPUTS
DATA OUTPUTS
DATA OUTPUTS
INPUT DATA VALID
OUTPUT DATA VALID
OUTPUT DATA VALID