
TSL201R
64 1 LINEAR SENSOR ARRAY
TAOS030B – AUGUST 2002
4
Copyright 2002, TAOS Inc.
The LUMENOLOGY Company
www.taosinc.com
Electrical Characteristics at f
clock
= 1 MHz, V
DD
= 5 V, T
A
= 25
°
C,
λ
p
= 640 nm, t
int
= 5 ms,
R
L
= 330
, E
e
= 16.5
μ
W/cm
2
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
out
V
drk
PRNU
Analog output voltage (white, average over 64 pixels)
see Note 1
1.6
2
2.4
V
Analog output voltage (dark, average over 64 pixels)
E
e
= 0
See Notes 2 & 3
0
50
120
mV
Pixel response nonuniformity
±
4%
±
0.4%
±
7.5%
Nonlinearity of analog output voltage
See Note 3
FS
Output noise voltage
See Note 4
1
mVrms
R
e
Responsivity
18
23
V/
(μ
J/cm
2
)
nJ/cm
2
SE
Saturation exposure
See Note 5
142
V
sat
DSNU
Analog output saturation voltage
2.5
3.4
V
Dark signal nonuniformity
All pixels, E
e
= 0
See Note 7
See Note 6
25
120
mV
IL
Image lag
0.5%
I
DD
I
IH
I
IL
C
i(SI)
Supply current, output idle
3.4
4
mA
μ
A
μ
A
pF
High-level input current
V
I
= V
DD
V
I
= 0
1
Low-level input current
1
Input capacitance, SI
5
C
i(CLK)
NOTES:
Input capacitance, CLK
5
pF
1. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
2. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
3. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
4. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
5. Minimum saturation exposure is calculated using the minimum V
sat
, the maximum V
drk
, and the maximum R
e
.
6. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination.
7. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
IL
Vout (IL)
Vout (white)
Vdrk
Vdrk
100
Timing Requirements (see Figure 1 and Figure 2)
MIN
NOM
MAX
UNIT
t
su(SI)
t
h(SI)
t
w
t
r
, t
f
NOTES:
Setup time, serial input (see Note 8)
20
ns
Hold time, serial input (see Note 8 and Note 9)
0
ns
Pulse duration, clock high or low
50
ns
Input transition (rise and fall) time
8. Input pulses have the following characteristics: t
r
= 6 ns, t
f
= 6 ns.
9. SI must go low before the rising edge of the next clock pulse.
0
500
ns
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
PARAMETER
TEST CONDITIONS
R
L
= 330
,
MIN
TYP
MAX
UNIT
t
s
Analog output settling time to
±
1%
C
L
= 10 pF
185
ns