參數(shù)資料
型號(hào)： TSC251G1DXXX-L16CED
英文描述： IC CYCLONE III FPGA 5K 256-UBGA
中文描述： 微控制器
文件頁數(shù)： 48/63頁
文件大?。?/td> 878K
代理商： TSC251G1DXXX-L16CED
48
Rev. A - May 7, 1999
TSC80251G2D
11.5 AC Characteristics - SSLC: I
2
C Interface
Timings
Table 53. I
2
C Interface AC Timing; V
DD
= 2.7 to 5.5 V, T
A
= -40 to 85
°
C
Notes:
1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1
μ
s.
3. Spikes on the SDA and SCL lines with a duration of less than 3·T
CLCL
will be filtered out. Maximum capacitance on bus-lines SDA and
SCL= 400 pF.
4. T
CLCL
= T
OSC
= one oscillator clock period.
Waveforms
Figure 26. I
2
C Waveforms
Symbol
Parameter
INPUT
Min
Max
OUTPUT
Min
Max
T
HD
; STA
Start condition hold time
14·T
CLCL(4)
16·T
CLCL(4)
14·T
CLCL(4)
4.0
μ
s
(1)
4.7
μ
s
(1)
4.0
μ
s
(1)
T
LOW
SCL low time
T
HIGH
SCL high time
T
RC
SCL rise time
1
μ
s
0.3
μ
s
-
(2)
T
FC
SCL fall time
0.3
μ
s
(3)
T
SU
; DAT1
Data set-up time
250 ns
20·T
CLCL(4)
- T
RD
1
μ
s
(1)
8·T
CLCL(4)
8·T
CLCL(4)
- T
FC
4.7
μ
s
(1)
4.0
μ
s
(1)
4.7
μ
s
(1)
T
SU
; DAT2
SDA set-up time (before repeated START condition)
250 ns
T
SU
; DAT3
SDA set-up time (before STOP condition)
250 ns
T
HD
; DAT
Data hold time
0 ns
14·T
CLCL(4)
14·T
CLCL(4)
14·T
CLCL(4)
T
SU
; STA
Repeated START set-up time
T
SU
; STO
STOP condition set-up time
T
BUF
Bus free time
T
RD
SDA rise time
1
μ
s
0.3
μ
s
-
(2)
T
FD
SDA fall time
0.3
μ
s
(3)
T
SU
;STA
T
SU
;DAT2
T
HD
;STA
T
HIGH
T
LOW
SDA
(INPUT/OUTPUT)
0.3 V
DD
0.7 V
DD
T
BUF
T
SU
;STO
0.7 V
DD
0.3 V
DD
T
RD
T
FD
T
RC
T
FC
SCL
(INPUT/OUTPUT)
T
SU
;DAT1
T
HD
;DAT
T
SU
;DAT3
START or Repeated START condition
START condition
STOP condition
Repeated START condition
相關(guān)PDF資料
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