參數(shù)資料
型號(hào)： TSC2301PAG
廠商： Texas Instruments, Inc.
英文描述： SIGN, EYE PROTECTION MUST BE WORN; RoHS Compliant: NA
中文描述： 可編程觸摸屏控制器，立體聲編解碼器
文件頁(yè)數(shù)： 76/92頁(yè)
文件大小： 1161K
代理商： TSC2301PAG
www.ti.com
TSC2301
SLAS371D–SEPTEMBER 2002–REVISED AUGUST 2004
Bits [7:6] — MCLK1-MCLK0
Master Clock Ratio. These two bits select the ratio of the audio master clock frequency to the audio sampling
frequency. The ratio can be 256 Fs, 384 Fs, or 512 Fs. The default master clock frequency is 256 Fs.
Table 35. Master Clock Ratio Selection
MCLK[1:0]
MCLK1
0
0
1
1
MCLK0
0
1
0
1
Description
Master clock (MCLK) = 256 x Fs (default)
Master clock (MCLK) = 384 x Fs
Master clock (MCLK) = 512 x Fs
Master clock (MCLK) = 256 x Fs
Bits [5:2] — I2SFS3-I2SFS0
I
2
S Sample Rate. These bits tell the internal PLL what the audio sampling rate is so that it provides the proper
clock rate to the data converters and the digital filters. The default sample rate is 48 kHz. See
Table 36
for a
complete listing of available sampling rates. All combinations of I2SFS[3:0] not in
Table 36
are not valid.
Table 36. I
2
S Sample Rate Select
I2SFS3
0
0
0
0
0
0
0
0
1
I2SFS2
0
0
0
0
1
1
1
1
0
I2SFS1
0
0
1
1
0
0
1
1
0
I2SFS0
0
1
0
1
0
1
0
1
0
Function
Fs = 48 kHz (default)
Fs = 44.1 kHz
Fs = 32 kHz
Fs = 24 kHz
Fs = 22.05 kHz
Fs = 16 kHz
Fs = 12 kHz
Fs = 11.05 kHz
Fs = 8 kHz
Bits [1:0] — I2SFM1-I2SFM0
I
2
S Format. These two bits select the I
2
S interface format. Both 16-bit and 20-bit data formats are supported. The
default format is 20-bit I
2
S.
Table 37. I
2
S Format Selection
I2SFM [1:0]
I2SFM1
0
0
1
1
I2SFM0
0
1
0
1
Description
DAC: 16-bit, MSB-first, right justified ADC: 16-bit, MSB-first, left justified
DAC: 20-bit, MSB-first, right justified ADC: 20-bit, MSB-first, left justified
DAC: 20-bit, MSB-first, left justified ADC: 20-bit, MSB-first, left justified
DAC: 20-bit, MSB-first, I
2
S (default) ADC: 20-bit, MSB-first, I
2
S (default)
ADC VOLUME CONTROL REGISTER (Page 2, Address 01h)
The ADC volume control register controls the independent programmable gain amplifiers (PGA's) on the left and
right channel inputs to the audio ADCs of the TSC2301. The gain of these PGAs can be adjusted from
-40 dB to 20 dB in 0.5-dB steps. The ADC inputs can also be
hard-muted
, or internally shorted to VCM so that no
input signal is seen.
The ADC volume control register is formatted as follows:
Bit 15
MSB
ADMU
L
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSB
ADVL
6
ADVL5
ADVL4
ADVL3
ADVL
2
ADVL
1
ADVL
0
ADMU
R
ADVR6 ADVR5 ADVR4 ADVR3 ADVR2 ADVR ADVR
1
0
76
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TSC2302IRGZR 功能描述:觸摸屏轉(zhuǎn)換器和控制器 Prog 4-Wire w/20-Bit Stereo Audio Codec RoHS:否 制造商:Microchip Technology 類型:Resistive Touch Controllers 輸入類型:3 Key 數(shù)據(jù)速率:140 SPS 分辨率:10 bit 接口類型:4-Wire, 5-Wire, 8-Wire, I2C, SPI 電源電壓:2.5 V to 5.25 V 電源電流:17 mA 工作溫度:- 40 C to + 85 C 封裝 / 箱體:SSOP-20
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