參數(shù)資料
型號(hào)： TSB41LV03AI
廠(chǎng)商： Texas Instruments, Inc.
英文描述： IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER
中文描述： IEEE 1394a連接三端口電纜收發(fā)器/仲裁者
文件頁(yè)數(shù)： 28/50頁(yè)
文件大?。?/td> 662K
代理商： TSB41LV03AI
SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
crystal selection (continued)
The following are some typical specifications for crystals used with the physical layers from TI in order to achieve
the required frequency accuracy and stability:
Crystal mode of operation: Fundamental
Frequency tolerance at 25
°
C: Total frequency variation for the complete circuit is
±
100 ppm. A crystal with
±
30-ppm frequency tolerance is recommended for adequate margin.
Frequency stability (over temperature and age): A crystal with
±
30-ppm frequency stability is recommended
for adequate margin.
NOTE:
The total frequency variation must be kept below
±
100 ppm from nominal with some allowance for
error introduced by board and device variations. Trade-offs between frequency tolerance and
stability may be made as long as the total frequency variation is less than
±
100 ppm. For example,
the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance
may be specified at 30 ppm to give a total of 80 ppm possible variation due to the crystal alone.
Crystal aging also contributes to the frequency variation.
Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent
upon the load capacitance specified for the crystal. Total load capacitance (C
L
) is a function of not only the
discrete load capacitors, but also board layout and circuit. It may be necessary to iteratively select discrete
load capacitors until the SYSCLK output is within specification. It is recommended that load capacitors with
a maximum of
±
5% tolerance be used.
For example, the OHCI + 41LV03 evaluation module (EVM), which uses a crystal specified for 12 pF loading,
uses load capacitors (C9 and C10 in Figure 11) of 16 pF each were appropriate for the layout of that particular
board. The load specified for the crystal includes the load capacitors (C9, C10), the loading of the PHY terminals
(C
PHY
), and the loading of the board itself (C
BD
). The value of C
PHY
is typically about 1 pF, and C
BD
is typically
0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more. The load capacitors C9 and
C10 combine as capacitors in series so that the total load capacitance is:
C
L
= [(C9
×
C10) / (C9+C10)] + C
PHY
+ C
BD
.
C10
X1
XI
XO
24.576 MHz
Is
C9
CPHY + CBD
Figure 11. Load Capacitance for the TSB41AB3 PHY
NOTE:
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency,
minimizing noise introduced into the PHY
’
s phase lock loop, and minimizing any emissions from
the circuit. The crystal and two load capacitors are considered as a unit during layout. The crystal
and load capacitors are placed as close as possible to one another while minimizing the loop area
created by the combination of the three components. Varying the size of the capacitors may help
in this. Minimizing the loop area minimizes the effect of the resonant current (Is) that flows in this
resonant circuit. This layout unit (crystal and load capacitors) must then be placed as close as
possible to the PHY XI and XO terminals to minimize trace lengths.
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參數(shù)描述
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TSB41LV03APFPG4 功能描述:1394 接口集成電路 THREE-PORT CABLE XCVR/ARBITER RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB41LV03PFP 制造商:Texas Instruments 功能描述:
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