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參數(shù)資料
| 型號： | TSB17BA1PW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE STD 1394b SINGLE-PORT CABLE TRANSCEIVER |
| 中文描述： | IEEE標準的1394b單端口電纜收發(fā)器 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 218K |
| 代理商： | TSB17BA1PW |
SLLS568C JANUARY 2004 REVISED MARCH 2004
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
TYPE
NO.
Test Terminals
E_INN
Test
2
I
Input reserved for future enhancement. Must be grounded for normal operation.
E_INP
Test
3
I
Input reserved for future enhancement. Must be grounded for normal operation.
E_OUT
Test
1
O
Output reserved for future enhancement. May be left unconnected for normal operation.
TEST0
TEST1
TEST2
TEST3
CMOS
11
12
13
14
I
Test control. These inputs are used in the manufacturing test of the TSB17BA1. For normal
use, these terminals must be pulled low to GND.
IEEE Std 1394b PHY Terminals
BETA_INP
BETA_INN
Input from
1394b
PHY
8
9
I
Input of ac-coupling block. These twisted-pair differential-signal terminals connect the
TSB17BA1 BETA_INP to the 1394b PHY TPB+ and BETA_INN to the 1394b PHY TPB
terminals of the port on the 1394b PHY. Board traces from each pair of positive and
negative differential signal terminals must be kept matched and as short as possible to the
external load resistors and to the 1394b PHY. The transmission lines between the 1394b
PHY and TSB17BA1 must be terminated properly.
BETA_OUTP
BETA_OUTN
Output to
1394b
PHY
5
6
O
Output of 1394b driver block. These twisted-pair differential-signal terminals, connect the
TSB17BA1 BETA_OUTP to the 1394b PHY TPA+ and BETA_OUTN to the 1394b PHY
TPA terminals of the port on the 1394b PHY. Board traces from each pair of positive and
negative differential signal terminals must be kept matched and as short as possible to the
external load resistors and to the 1394b PHY. The transmission lines between the 1394b
PHY and TSB17BA1 must be terminated properly.
RJ45 Terminals
UTP5_INN
Input from
UTP5
Cable
19
I
Negative differential side of input from the UTP5 cable to the TSB17BA1 termination
network. Connect to network corresponding to RJ45 pin number 6 or RJ45 pin number 8.
UTP5_INP
Input from
UTP5
Cable
20
I
Positive differential side of input from the UTP5 cable to the TSB17BA1 termination
network. Connect to network corresponding to RJ45 pin number 3 or RJ45 pin number 7.
UTP5_OUTN
Output to
UTP5
Cable
16
O
Negative differential side of output from TSB17BA1 to the UTP5 cable termination network.
Connect to network corresponding to RJ45 pin number 2.
UTP5_OUTP
Output to
UTP5
Cable
17
O
Positive differential side of output from TSB17BA1 to the UTP5 cable termination network.
Connect to network corresponding to RJ45 pin number 1.
Power and Ground Terminals
PD_SE
CMOS
10
I/O
Global power down. A high on this terminal turns off all internal circuitry.
R0
Bias
21
Current setting resistor. This terminal is connected to a precision external resistance to set
the internal operating currents and the cable-driver output currents. This terminal has a
very low impedance to ground.
R1
Bias
22
I
Current setting resistor (band-gap sense voltage). This terminal is connected to a precision
external resistance to set the internal operating currents and the cable-driver output
currents. A resistance of 6.04 k
,
1% between R0 and R1, is required to meet the 1394b
output-voltage limits.
VCONTROL
23
I/O
Voltage control (reserved). Nominally not connected.
VREG_PD
CMOS
24
I
Power down for voltage regulator. When driven low, the device uses an internal regulator to
generate the required 1.8 V. When driven high, the internal regulator is powered down and
the 1.8 V must be supplied externally to power the 1.8-V circuitry of the device. Nominally
tied low to enable the internal regulator.
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| TSB17BA1PWG4 | 功能描述:1394 接口集成電路 UTP5 Equalizer for 1394b PHYs RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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| TSB2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EURO TERMINAL BLOCKS |
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