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參數(shù)資料
| 型號(hào)： | TSB12C01AWN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed Serial-Bus Link-Layer Controller |
| 中文描述： | 高速串行總線鏈路層控制器 |
| 文件頁(yè)數(shù)： | 17/59頁(yè) |
| 文件大?。?/td> | 275K |
| 代理商： | TSB12C01AWN |
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3–1
3 Internal Registers
3.1
General
The host-bus processor directs the operation of the TSB12C01A through a set of registers internal to the
TSB12C01A itself. These registers are read or written by asserting CS with the proper address on ADDR0
– ADDR7 and asserting or deasserting WR depending on whether a read or write is needed. Figure 3–1 lists
the register addresses; subsequent sections describe the function of the various registers.
3.2
The TSB12C01A internal registers control the operation of the TSB12C01A. The bit definitions of the internal
registers are shown in Figure 3–1 and are described in subsections 3.2.1 through 3.2.13.
Internal Register Definitions
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參數(shù)描述 |
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