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    參數(shù)資料
    型號(hào): TS87C51RD2-MCE
    廠商: Atmel
    文件頁(yè)數(shù): 59/84頁(yè)
    文件大小: 0K
    描述: IC MCU 8BIT 64K OTP 40MHZ 44VQFP
    標(biāo)準(zhǔn)包裝: 160
    系列: 87C
    核心處理器: 8051
    芯體尺寸: 8-位
    速度: 40/20MHz
    連通性: UART/USART
    外圍設(shè)備: POR,PWM,WDT
    輸入/輸出數(shù): 32
    程序存儲(chǔ)器容量: 64KB(64K x 8)
    程序存儲(chǔ)器類型: OTP
    RAM 容量: 1K x 8
    電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
    振蕩器型: 內(nèi)部
    工作溫度: 0°C ~ 70°C
    封裝/外殼: 44-QFP
    包裝: 托盤
    dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
    DS70292G-page 64
    2007-2012 Microchip Technology Inc.
    4.6.3
    MODULO ADDRESSING
    APPLICABILITY
    Modulo Addressing can be applied to the Effective
    Address (EA) calculation associated with any W
    register. Address boundaries check for addresses
    equal to:
    The upper boundary addresses for incrementing
    buffers
    The lower boundary addresses for decrementing
    buffers
    It is important to realize that the address boundaries
    check for addresses less than or greater than the upper
    (for incrementing buffers) and lower (for decrementing
    buffers) boundary addresses (not just equal to).
    Address changes can, therefore, jump beyond
    boundaries and still be adjusted correctly.
    4.7
    Bit-Reversed Addressing
    Bit-Reversed Addressing mode is intended to simplify
    data reordering for radix-2 FFT algorithms. It is
    supported by the X AGU for data writes only.
    The modifier, which can be a constant value or register
    contents, is regarded as having its bit order reversed.
    The address source and destination are kept in normal
    order. Thus, the only operand requiring reversal is the
    modifier.
    4.7.1
    BIT-REVERSED ADDRESSING
    IMPLEMENTATION
    Bit-Reversed Addressing mode is enabled in any of
    these situations:
    BWM bits (W register selection) in the MODCON
    register are any value other than ‘15’ (the stack
    cannot be accessed using Bit-Reversed
    Addressing)
    The BREN bit is set in the XBREV register
    The addressing mode used is Register Indirect
    with Pre-Increment or Post-Increment
    If the length of a bit-reversed buffer is M = 2N bytes,
    the last ‘N’ bits of the data buffer start address must
    be zeros.
    XB<14:0> is the Bit-Reversed Address modifier, or
    ‘pivot point,’ which is typically a constant. In the case of
    an FFT computation, its value is equal to half of the FFT
    data buffer size.
    When enabled, Bit-Reversed Addressing is executed
    only for Register Indirect with Pre-Increment or Post-
    Increment Addressing and word-sized data writes. It
    does not function for any other addressing mode or for
    byte-sized data, and normal addresses are generated
    instead. When Bit-Reversed Addressing is active, the
    W Address Pointer is always added to the address
    modifier (XB), and the offset associated with the
    Register Indirect Addressing mode is ignored. In
    addition, as word-sized data is a requirement, the LSb
    of the EA is ignored (and always clear).
    If Bit-Reversed Addressing has already been enabled
    by setting the BREN bit (XBREV<15>), a write to the
    XBREV register should not be immediately followed by
    an indirect read operation using the W register that has
    been designated as the bit-reversed pointer.
    Note:
    The modulo corrected effective address is
    written back to the register only when Pre-
    Modify or Post-Modify Addressing mode is
    used to compute the effective address.
    When an address offset (such as [W7 +
    W2]) is used, Modulo Address correction
    is performed but the contents of the
    register remain unchanged.
    Note:
    All bit-reversed EA calculations assume
    word-sized data (LSb of every EA is
    always clear). The XB value is scaled
    accordingly to generate compatible (byte)
    addresses.
    Note:
    Modulo Addressing and Bit-Reversed
    Addressing
    should
    not
    be
    enabled
    together. If an application attempts to do so,
    Bit-Reversed Addressing assumes priority
    when active for the X WAGU and X WAGU,
    Modulo Addressing is disabled. However,
    Modulo Addressing continues to function in
    the X RAGU.
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