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      參數(shù)資料
      型號: TS87C51RC2-MCE
      廠商: Atmel
      文件頁數(shù): 28/84頁
      文件大小: 0K
      描述: IC MCU 8BIT 32K OTP 40MHZ 44VQFP
      標準包裝: 160
      系列: 87C
      核心處理器: 8051
      芯體尺寸: 8-位
      速度: 40/20MHz
      連通性: UART/USART
      外圍設備: POR,PWM,WDT
      輸入/輸出數(shù): 32
      程序存儲器容量: 32KB(32K x 8)
      程序存儲器類型: OTP
      RAM 容量: 512 x 8
      電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
      振蕩器型: 內(nèi)部
      工作溫度: 0°C ~ 70°C
      封裝/外殼: 44-QFP
      包裝: 托盤
      dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
      DS70292G-page 36
      2007-2012 Microchip Technology Inc.
      4.1.1
      PROGRAM MEMORY
      ORGANIZATION
      The program memory space is organized in word-
      addressable blocks. Although it is treated as 24 bits
      wide, it is more appropriate to think of each address of
      the program memory as a lower and upper word, with
      the upper byte of the upper word being unimplemented.
      The lower word always has an even address, while the
      upper word has an odd address (Figure 4-2).
      Program memory addresses are always word-aligned
      on the lower word, and addresses are incremented or
      decremented by two during code execution. This
      arrangement provides compatibility with data memory
      space addressing and makes data in the program
      memory space accessible.
      4.1.2
      INTERRUPT AND TRAP VECTORS
      All dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
      X04, and dsPIC33FJ128GPX02/X04 devices reserve
      the addresses between 0x00000 and 0x000200 for
      hard-coded program execution vectors. A hardware
      Reset vector is provided to redirect code execution
      from the default value of the PC on device Reset to the
      actual start of code. A GOTO instruction is programmed
      by the user application at 0x000000, with the actual
      address for the start of code at 0x000002.
      dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
      and dsPIC33FJ128GPX02/X04 devices also have two
      interrupt vector tables, located from 0x000004 to
      0x0000FF and 0x000100 to 0x0001FF. These vector
      tables allow each of the device interrupt sources to be
      handled by separate Interrupt Service Routines (ISRs).
      A more detailed discussion of the interrupt vector
      tables is provided in Section 7.1 “Interrupt Vector
      FIGURE 4-2:
      PROGRAM MEMORY ORGANIZATION
      0
      8
      16
      PC Address
      0x000000
      0x000002
      0x000004
      0x000006
      23
      00000000
      Program Memory
      ‘Phantom’ Byte
      (read as ‘0’)
      least significant word
      most significant word
      Instruction Width
      0x000001
      0x000003
      0x000005
      0x000007
      msw
      Address
      (lsw Address)
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