參數(shù)資料
型號: TS87C51RB2-VIA
廠商: Atmel
文件頁數(shù): 1/3頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 16K OTP 40MHZ 40-DIP
標(biāo)準(zhǔn)包裝: 9
系列: 87C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40/30MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: OTP
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
Active Errata List
UART/Reception in Modes 1, 2 and 3/UART False Start Bits Detection
During UART Reception, Clearing REN May Generate Unexpected IT
JBC/Double IT When External IT Occurs During JBC Instruction
Timer2/Downcounter Mode/Double IT With Slow External Clock
Input Trigger Consumption/All C51 Type I/O Ports
MOVX/Port0/Read Mode
Errata History
AT80C51RA2
TS80C51RB2
TS87C51RB2
Errata Descriptions
1.
UART/Reception in Modes 1, 2 and 3/UART False Start Bits Detection
When a false start bit occurs on the UART, some UART internal signals are not reset.
Then when a real start bit occurs, the sampling is shifted.
Workaround
None.
2.
During UART Reception, Clearing REN May Generate Unexpected IT
During UART reception, if the REN bit is clear between a start bit detection and the
end of reception, the UART will not discard the data (RI is set).
Workaround
Test REN at the beginning of Interrupt routine just after CLR RI, and run the Interrupt
routine code only if REN is set.
Lot Number
Errata List
All
T02,T03,T04,T05,T06
Lot Number
Errata List
≤ 38584
T01, T02 ,T03, T04, T05, T06
> 38584
T02 ,T03, T04, T05, T06
Lot Number
Errata List
≤ 36425
T01, T02 ,T03, T04, T05, T06
> 36425
T02 ,T03, T04, T05, T06
8051
Microcontrollers
TS87C51RB2
TS80C51RB2
AT80C51RA2
Errata Sheet
4154D–8051–03/08
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