參數(shù)資料
型號: TS8308500CG
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA72
封裝: 1.27 MM PITCH, HEAT SINK, CERAMIC, BGA-72
文件頁數(shù): 42/42頁
文件大小: 641K
代理商: TS8308500CG
9
Preliminary Specification
ββββ-site
TS8308500
3.4.
TIMING DIAGRAMS
Figure 1: TS8308500 TIMING DIAGRAM (500 MSPS CLOCK RATE)
Data Ready Reset, Clock Held at LOW Level
Figure 2: TS8308500 TIMING DIAGRAM (500 MSPS CLOCK RATE)
Data Ready Reset, Clock Held at HIGH Level
DATA
READY
DR / DRB
TD2 = TC2 + TOD – TDR
= TC2 + 40 ps = 1040 ps
N
TA = 250 ps
TD1 = TC1 + TDR – TOD
= TC1 – 40 ps = 960 ps
TC2
TC1
TC = 2 ns
TPD = 4.0 Clock Periods
TOD = 1360 ps
TDR = 1320 ps
2 ns
1360 ps
TDR = 1320 ps
TRDR = 720 ps
1 ns
N
N -5
N -4
N -3
N -2
N -1
N + 1
N+3
N+2
N + 1
CLK / CLKB
VIN / VINB
Digital
OUTPUTS
DATA READY
RESET
TD2 = TC2 + TOD – TDR
= TC2 + 40 ps = 1040 ps
TD1 = TC1 + TDR – TOD
= TC1 – 40 ps = 960 ps
TDR = 1320 ps
1 ns
TRDR = 720 ps
DATA READY
RESET
DATA
READY
DR / DRB
TDR = 1320 ps
CLK / CLKB
N
TA = 250 ps
TC2
TC1
TC = 2 ns
N + 3
N + 2
N + 1
VIN / VINB
2 ns
Digital
OUTPUTS
TPD = 4.0 Clock Periods
TOD = 1360 ps
1360 ps
N
N -5
N -4
N -3
N -2
N -1
N + 1
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