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  • 參數(shù)資料
    型號(hào): TS80C31X2-VCBB
    廠商: ATMEL CORP
    元件分類: 微控制器/微處理器
    英文描述: 8-bit CMOS Microcontroller ROMless
    中文描述: 8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
    封裝: PLASTIC, LCC-44
    文件頁數(shù): 25/40頁
    文件大小: 484K
    代理商: TS80C31X2-VCBB
    Rev. A - Mar. 19, 1999
    25
    Preliminary
    TS80C31X2
    6.8 Power-Off Flag
    The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset.
    A cold start reset is the one induced by V
    CC
    switch-on. A warm start reset occurs while V
    CC
    is still applied to
    the device and could be generated for example by an exit from power-down.
    The power-off flag (POF) is located in PCON register (See Table 13.). POF is set by hardware when V
    CC
    rises
    from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type
    of reset.
    Table 13. PCON Register
    PCON - Power Control Register (87h)
    7
    Reset Value = 00X1 0000b
    Not bit addressable
    6
    5
    4
    3
    2
    1
    0
    SMOD1
    SMOD0
    -
    POF
    GF1
    GF0
    PD
    IDL
    Bit
    Number
    Bit
    Mnemonic
    Description
    7
    SMOD1
    Serial port Mode bit 1
    Set to select double baud rate in mode 1, 2 or 3.
    6
    SMOD0
    Serial port Mode bit 0
    Clear to select SM0 bit in SCON register.
    Set to to select FE bit in SCON register.
    5
    -
    Reserved
    The value read from this bit is indeterminate. Do not set this bit.
    4
    POF
    Power-Off Flag
    Clear to recognize next reset type.
    Set by hardware when V
    CC
    rises from 0 to its nominal voltage. Can also be set by software.
    3
    GF1
    General purpose Flag
    Cleared by user for general purpose usage.
    Set by user for general purpose usage.
    2
    GF0
    General purpose Flag
    Cleared by user for general purpose usage.
    Set by user for general purpose usage.
    1
    PD
    Power-Down mode bit
    Cleared by hardware when reset occurs.
    Set to enter power-down mode.
    0
    IDL
    Idle mode bit
    Clear by hardware when interrupt or reset occurs.
    Set to enter idle mode.
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