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參數(shù)資料
| 型號： | TS3843BCS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Current Mode Controller |
| 中文描述： | 高性能電流模式控制器 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大小： | 521K |
| 代理商： | TS3843BCS |
Current Sense Comparator and PWM Latch
The TS3842B operate as a current mode controller, whereby output switch conduction is initiated
by the oscillator and terminated when the peak inductor current reaches the threshold level estab-
lished by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the peak
inductor current on a cycle-by-cycle basis. The Current Sense Comparator PWM Latch configu-
ration used ensures that only a single appears at the Output during any given oscillator cycle. The
inductor current is converted to a voltage by inserting the ground referenced sense resistor R
in
series with the source of output switch Q1. This voltage is monitored by the Current Sense Input
(Pin 3) and compared to a level derived from the Error Amp Output. The peak inductor current
under normal operating conditions is controlled by the voltage at pin 1 where:
I
PK
= [V(Pin 1) - 1.4V] / 3R
S
Abnormal operating conditions occur when the power supply output is overloaded or if output
voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be
internally clamped to 1.0V. Therefore the maximum peak switch current is:
I
PK (MAX)
= 1.0V / R
S
When designing a high power switching regulator it becomes desirable to reduce the internal
clamp voltage in order to keep the power dissipation of R
to a reasonable level. A simple method
to adjust this voltage is shown in Figure 22. The two external diodes are used to compensate the
internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to noise
pickup can result if there is an excessive reduction of the I
PK
(max) clamp voltage.
A narrow spike on the leading edge of the current waveform can usually be observed and may
cause the power supply to exhibit an instability when the output is lightly loaded. This spike is
due to the power transformer interwinding capacitance and output rectifier recovery time. The
addition of an RC filter on the Current Sense Input with a time constant that approximates the
spike duration will usually eliminate the instability: refer to Figure 26.
R
f(MIN)
= [3x(1.0V)+1.4V] / 0.5mA = 8800
the load is removed, or at the beginning of a soft-start interval (Figure 23,24). The Error Amp
minimum feedback resistance is limited by the amplifier’s source current (0.5mA) and the re-
quired output voltage (V
OH
) to reach the comparator’s 1.0V clamp level:
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