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參數(shù)資料
| 型號： | TRU050-TFCGA65.536-1.024 |
| 廠商： | VECTRON INTERNATIONAL |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, CDIP16 |
| 封裝： | HERMETIC SEALED, CERAMIC, DIP-16 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 627K |
| 代理商： | TRU050-TFCGA65.536-1.024 |
Vectron International 166 Glover Avenue, Norwalk, CT 06856-5160 Tel: 1-88-VECTRON-1 e-mail: vectron@vectron.com
A typical PLL is illustrated in figure 12. Be advised that many textbook equations describing loop dynamics, such as capture range or lockin time, are based on ideal systems.
Such equations may not be accurate for real systems with nonlinearities, DC offsets and noise. A PLL is a feedback system which forces the output frequency to lockin both
phase and frequency to the fundamental frequency of the input signal.
When initially out of lock, the output of the phase detector is proportional to the difference in frequency between the two phase detector inputs. This beat note varies the
output frequency of the VCXO, and in a properly designed phase-locked loop, the loop action forces Vc to the correct value to bring the system into lock.
A designer’s primary concern is to select a loop filter that ensures lockin and stability, while providing adequate
filtering of input signal noise or jitter. An initial design starts with a known DATAIN signal and an output
specification. An initial analysis of the open loop gain response provides insight into the response of the system.
Using figure 12, the open loop gain is:
G(s)= Kp kV AV(s)
sN
Where:
Kp is the phase detector gain in V/rad (-0.53 x Data Density).
kV is the VCXO gain constant in Rad/Vs.
AV(s) is the loop filter transfer function.
N is the divide ratio.
1/s converts the VCXO frequency output to a phase output.
The open loop gain may be plotted and varied using the SPICE model provided in figure 13. The gain, frequency,
and loop filter configurations may be varied to producedesired responses. In the first-order phase-locked loop,
where AV(s) and N equal 1, the gain curve has a 20 dB/decade slope with unity gain at:
f = kV Kp where kV is in rad/Vs.
2
π
Figure 12.
10 of 17
How Does It Perform?
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TRU050-TFCGA-65M0000000 | 制造商:VECTRON 制造商全稱:Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
| TRU050-TFCGB-1M0000000 | 制造商:VECTRON 制造商全稱:Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
| TRU050-TFCGB-65M0000000 | 制造商:VECTRON 制造商全稱:Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
| TRU050-TFCHA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE DROP IN QUARTZ STABILIZED PLL SOLUTUION |
| TRU050-TFCHA-1M0000000 | 制造商:VECTRON 制造商全稱:Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
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