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參數(shù)資料
| 型號(hào)： | TRU050-TBLCA32.000-8.000 |
| 廠商： | VECTRON INTERNATIONAL |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, CDIP16 |
| 封裝： | HERMETIC SEALED, CERAMIC, DIP-16 |
| 文件頁(yè)數(shù)： | 14/17頁(yè) |
| 文件大?。?/td> | 627K |
| 代理商： | TRU050-TBLCA32.000-8.000 |
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LOS and LOSIN
The LOS circuit provides an output alarm flag when the DATAIN input signal is lost. The LOS output is set “l(fā)ogic high” after 256 consecutive CLKIN periods with no DATAIN
transitions. This signal can then be used to either flag external alarm circuits and/or drive the TRU-050’s LOSIN circuit. When the LOSIN input is set “l(fā)ogic high,” the loop
filter op-amp output is set mid supply to facilitate fast lockup when DATAIN is restored. In addition, the VCXO control voltage is internally set to hold the VCXO at its nominal
frequency (±75 ppm). When LOSIN is low or has no connection, the VCXO’s control voltage input is enabled (LOSIN has an internal pull-down resistor).
Loop Fi lter
Although various loop filter configurations may be considered, most TRU-050 applications use the basic integrator filter of figure 10. This type of filter provides high DC
gain to ensure proper clock and data alignment. The ratio of R1 to RF sets midband gain and can be used to adjust the loop bandwidth. The time constant, set by RF and
CF, should be selected to be about one decade below the open loop
bandwidth to provide good phase margin. The reference for the non-
inverting input is set at midsupply by R2 and R3. Software is available
to help in the selection of R1, CF and RF.
Vectron International 166 Glover Avenue, Norwalk, CT 06856-5160 Tel: 1-88-VECTRON-1 e-mail: vectron@vectron.com
Phase Detector Gain = [5V/2
π] * [2/3] * D = 0.53 * D
Where D = input data transition density. For example D = 1 for 100% transition density (e.g., clock signal)
and D = 0.5 for 50% transition density (e.g., balanced NRZ data).
Figure 9.
Figure 10.
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PDF描述 |
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| TRU050-TDLHA49.408-3.088 | PHASE LOCKED LOOP, CDIP16 |
| TRU050-TELHA32.000-1.000 | PHASE LOCKED LOOP, CDIP16 |
| TRU050-TFCGA65.536-1.024 | PHASE LOCKED LOOP, CDIP16 |
| TLVH431AIDBVRG4 | 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 1.24 V, PDSO5 |
| TLVH431BIDBVTG4 | 1-OUTPUT THREE TERM VOLTAGE REFERENCE, 1.24 V, PDSO5 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TRU050-TBLFA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE DROP IN QUARTZ STABILIZED PLL SOLUTUION |
| TRU050-TBLGA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE DROP IN QUARTZ STABILIZED PLL SOLUTUION |
| TRU050-TBLGA-1M0000000 | 制造商:VECTRON 制造商全稱:Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
| TRU050-TBLGA-65M0000000 | 制造商:VECTRON 制造商全稱:Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
| TRU050-TBLGB-1M0000000 | 制造商:VECTRON 制造商全稱:Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
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