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參數(shù)資料
| 型號(hào)： | TRU050-TACGA17.920-8.960 |
| 廠商： | VECTRON INTERNATIONAL |
| 元件分類(lèi)： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, CDIP16 |
| 封裝： | HERMETIC SEALED, CERAMIC, DIP-16 |
| 文件頁(yè)數(shù)： | 12/17頁(yè) |
| 文件大?。?/td> | 627K |
| 代理商： | TRU050-TACGA17.920-8.960 |
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Vectron International 166 Glover Avenue, Norwalk, CT 06856-5160 Tel: 1-88-VECTRON-1 e-mail: vectron@vectron.com
Phase Detector
The phase detector is designed to accept an NRZ data stream at DATAIN (Pin 7- refer to figure 5), but may be used
for clock signals and other data types. The input buffers are designed to switch at a TTL switching threshold of 1.4 V.
The phase detector’s inputs are:
DATAIN (Pin 7) - the input clock or NRZ data signal
CLKIN (Pin 9) - the clock signal feedback from the VCXO output OUT1 or OUT2
And the outputs are:
RCLK (Pin 11) - the regenerated clock signal
RDATA (Pin 12) - the retimed data signal
PHO (Pin 6) - the phase detector output
LOS (Pin 10) - a loss of signal detector
The phase relationship between the regenerated clock signal, RCLK (Pin 11), and the regenerated data signal,
RDATA (Pin 12), is shown in figure 6.
Figure 4.
4 of 17
The TRU-050 is a user-configured phase-locked loop (PLL) integrated circuit. It includes a voltage controlled crystal oscillator (VCXO), an operational amplifier, a phase
detector, and additional integrated functions for use in digital synchronization applications. These applications include timing recovery and data pulse restoration for data
signals, clock frequency translation and smoothing, synchronous distributed clock networks, and clock frequency synthesis.
How Is It Built?
TRU-050 Elements
What is the output of the
phase detector?
The TRU-050 phase detector output
is a DC signal, under locked
conditions, and is nominally 2.5
Volts. The phase error (which is
typically a pulse for digital phase
detectors) is converted to a DC
level, making it easy to design
the loop filter.
How long does the
TRU-050 take to detect
a loss of signal?
If there are no transitions on
DATAIN for a period of 256 clock
cycles, LOS is set to a logic 1.
LOS is reset to logic 0 as soon as
there are DATAIN transitions.
相關(guān)PDF資料 |
PDF描述 |
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| TRU050-TACGA47.457-23.7285 | PHASE LOCKED LOOP, CDIP16 |
| TRU050-TALFA12.288-6.144 | PHASE LOCKED LOOP, CDIP16 |
| TRU050-TBLCA32.000-8.000 | PHASE LOCKED LOOP, CDIP16 |
| TRU050-TDLHA49.408-3.088 | PHASE LOCKED LOOP, CDIP16 |
| TRU050-TELHA32.000-1.000 | PHASE LOCKED LOOP, CDIP16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TRU050-TACGA-1M0000000 | 制造商:VECTRON 制造商全稱(chēng):Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
| TRU050-TACGA-65M0000000 | 制造商:VECTRON 制造商全稱(chēng):Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
| TRU050-TACGB-1M0000000 | 制造商:VECTRON 制造商全稱(chēng):Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
| TRU050-TACGB-65M0000000 | 制造商:VECTRON 制造商全稱(chēng):Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
| TRU050-TACHA | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SINGLE DROP IN QUARTZ STABILIZED PLL SOLUTUION |
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