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參數(shù)資料
| 型號(hào)： | TRU050-GACFA17.920-8.960 |
| 廠商： | VECTRON INTERNATIONAL |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, CDSO16 |
| 封裝： | HERMETIC SEALED, GULL WING, CERAMIC, SMT, DIP-16 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 627K |
| 代理商： | TRU050-GACFA17.920-8.960 |
Timing Recover y Using OUT2
Due to the limitations in crystal size, the lowest frequency from OUT1 is 12 MHz. For applications below this
frequency, the internal divide-by can be used (Note: an additional external divide-by can also be used). An
application for 1.544 MHz clock recovery is shown in figure 19.
Vectron International 166 Glover Avenue, Norwalk, CT 06856-5160 Tel: 1-88-VECTRON-1 e-mail: vectron@vectron.com
Figure 18.
Figure 19.
RCLK
RDATA
14 of 17
Frequency Translation
The TRU-050 is most commonly used for frequency translation. For example, in a telecommunications
application, when a 2.048 MHz reference clock is multiplied to 32.768 MHz, a very clean 32.768 MHz clock
would then be output to other circuits.
Generally, the TRU-050 is specified in terms of NRZ input. Since the TRU-050’s phase detector was designed
for NRZ data, other inputs such as a clock signal should be considered as an equivalent 1010...NRZ pattern.
Eye Diagram for
TRU-050 @ 51.84 MHz
The falling edge of RCLK
is centered with respect
to RDATA
Ch. 1
=
1.000
Volts/div
Offset
=
9/6.2
mVolts
Ch. 2
=
1.000
Volts/div
Offset
=
951.2
mVolts
Timebase
=
3.000
ns/div
Delay
=
16.0000 ns
16.000 ns
31.0000 ns
46.0000 ns
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| TRU050-GACFA41.2416-20.6208 | PHASE LOCKED LOOP, CDSO16 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TRU050GACGA | 制造商:Vectron International 功能描述: |
| TRU050-GACGA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE DROP IN QUARTZ STABILIZED PLL SOLUTUION |
| TRU050-GACGA-1M0000000 | 制造商:VECTRON 制造商全稱:Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
| TRU050GACGA20.4800MHZ | 制造商:Vectron International 功能描述: |
| TRU050-GACGA-20M100 | 制造商:Vectron International 功能描述:Clock Data Recovery, 20.1MHz, 5V, SMD, CMOS, 50ppm, Bulk |
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