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參數資料
| 型號： | TQ8224 |
| 英文描述： | Industrial Control IC |
| 中文描述： | 工業(yè)控制IC |
| 文件頁數： | 9/22頁 |
| 文件大?。?/td> | 210K |
| 代理商： | TQ8224 |
TQ8223
PRELIMINARY DATA SHEET
9
S
P
T
P
Table 1. Signal Description (continued)
Pin No.
Grid Ref. Signal
8
C13
CKIN
Type and Freq. or Bit Rate
Input AC
2.48832 GHz
Description
High frequency clock input. The differential inputs must be
AC coupled and externally terminated by R
Te
to V
TTe
.
Must
be externally terminated by 10k
to VEE when internal
VCO is used.
Complement of CKIN.
Must be left open when internal VCO
is used.
38.88 MHz PECL hint clock to aid PLL acquistion.
High speed clock monitor. 30mVpp with a 50
load.
Clock select signal for choosing between external or internal
clock source as the active clock. NC =Internal VCO;
V
EE
= External VCO. When external VCO is chosen, the
internal VCO is forced to a fixed logic state even if powered.
Phase detector output. Requires external pull-up resistor to
V
DD
.
Phase detector reference output. Requires external pull-up
resistor to V
DD
.
Phase detector static offset. Nominally at 2.1V. The full range
of 2.1 +/- 0.625 V produces a -/+125 ps offset between the
center of the data eye and the falling edge of the sampling
clock. PHADJ has an internal default of 2.1V.
Internal PLL charge pump output.
Internal PLL lock detector. Remains high when frequency
difference between internal and external reference clocks is
less than 488 ppm. Accuracy of LOCK detect circuitry is
related to the accuracy of the external HINTCLK. Can be tied
to LOCKREF.
Forces internal PLL to lock to external reference clock when
LOCKREF is low.
LOCK signal lower hysterisis level. When PPMSEL=VDD the
LOCK signal will return to a high state when the frequency
difference between the internal and external reference clocks
is less than 122 ppm from HINTCLK. When PPMSEL=VEE the
LOCK will return to a high state when the frequency
difference is less than 30 ppm from HINTCLK.
7
B15
NCKIN
Input AC
2.48832 GHz
164
176
199
T17
M17
F17
HINTCLK Input PECL
HCKOUT
Output AC 2.48832 GHz
CLKSEL
Input
DC
12
B12
PHREF
Output Analog
11
B13
DCREF
Output Analog
183
J15
PHADJ
Input Analog
180
194
L17
F16
VTUNEO
LOCK
Output Analog
Output TTL
195
G17
LOCKREF Input TTL
200
E15
PPMSEL
Input TTL
Power Pins and Test Pins
202
D17
RSTN
Input PECL
Chip reset (active low) Normally tied to RESET.
When not
used must be tied to VDD through R
Te
Slips demultiplexer 1 Bit at each negative edge, can be used
once every 3ns.
When not used must be tied to VTT.
When PARSEL=N.C. parity bits generated are even. When
PARSEL=VEE parity bits generated are odd.
201
E17
SLIP
PECL
162
R16
PARSEL
TTL
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