參數(shù)資料
型號: TPU3050PO
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
元件分類: 圖文
英文描述: TELETEXT DECODER, PDIP52
封裝: SHRINK, PLASTIC, DIP-52
文件頁數(shù): 42/72頁
文件大?。?/td> 576K
代理商: TPU3050PO
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
47
4.10. Memory Manager
The Memory manager is the core of the internal
TPU 3040 software. Most of the acquisition and display
related functions are controlled by this management.
Acquisition
Scratch
Memory
Display
Memory
Display
Controller
Page
Memory
Page
Table
Memory
Manager
Fig. 4–7: Memory Manager
4.11. Memory Organization
The upper end of the memory is defined by the DRAM
size,
the
lower
end
can
be
defined
with
the
PAGE_MEMORY command. Default memory organiza-
tion is shown in Fig. 4–8.
Fig. 4–8: Memory Organization
DRAM
Acquisition
Scratch
Page Table
4 KByte
Display Bank
4 KByte
Page Memory
n x 1 KByte
00 00 00
00 10 00
00 20 00
00 30 00
TTX Display Bank
4 KByte
00 40 00
02 00 00 = 1Mbit
08 00 00 = 4Mbit
20 00 00 = 16Mbit
00 80 00 = 256Kbit
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