參數(shù)資料
型號: TPS65170RHDT
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: 4.2 A SWITCHING REGULATOR, 900 kHz SWITCHING FREQ-MAX, PQCC28
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-28
文件頁數(shù): 17/35頁
文件大?。?/td> 4698K
代理商: TPS65170RHDT
DLY
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DLY
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SLVSA27 – OCTOBER 2009
www.ti.com
Table 7. Negative Charge Pump Diode Selection
PART NUMBER
IAVG
IPK
VR
VF
COMPONENT SUPPLIER
BAV99W
150mA
1A for 1ms
75V
1V at 50mA
NXP
BAT54S
200mA
600mA for 1s
30V
0.8V at 100mA
Fairchild Semiconductor
MBR0540
500mA
5.5A for 8ms
40V
0.51 at 500mA
Fairchild Semiconductor
Selecting the Capacitors (Negative Charge Pump)
For lowest output voltage ripple, low-ESR ceramic capacitors are recommended. The actual value is not critical
and 1F to 10F is suitable for most applications. Larger capacitors provide better performance in applications
where large load transient currents are present.
A flying capacitor in the range 100nF to 1F is suitable for most applications. Larger values experience a smaller
voltage drop by the end of each switching cycle, and allow higher output voltages and/or currents to be achieved.
Smaller values tend to be physically smaller and cheaper.
A collector capacitor in the range 100nF to 1F is suitable for most applications. Larger values are more suitable
for high current applications but can affect stability.
A combination of COUT = 10 F, CFLY = 1F, and CCOLLECTOR = 100nF is a good starting point for most
applications (the final values can be optimized on a case-by-case basis if necessary).
POWER SUPPLY SEQUENCING
Figure 31 shows the power supply sequencing block diagram. The four supply rails generated by the TPS65170
turn on the following sequence: first VLOGIC, then VGL, then VGH and VS, as shown in Figure 31.
The buck converter turns on when the supply voltage exceeds the undervoltage threshold.
When the buck converter’s internal power good signal has been asserted, the reset timer starts; after the reset
time is over, RESET goes high and the negative charge pump is enabled. This sequence ensures that the
negative charge pump, which is driven by the switch node of the buck converter, does not attempt to draw
current until the T-CON is out of reset and drawing current from VLOGIC.
At the same time as the negative charge pump is enabled, an internal delay timer is started. This timer generates
a delay, after which the boost converter and positive charge pump are enabled. The delay time tDLY is
determined by the capacitor CDLY connected between the DLY pin and AGND according to Equation 29.
(29)
No special sequencing is implemented during power-down, and all power supplies are disabled if VIN falls below
VUVLO.
Figure 31. Power Supply Sequencing Block Diagram
24
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS65170
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