參數(shù)資料
型號： TPS65040ZQER
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA71
封裝： 5 X 5 MM, 0.50 MM PITCH, GREEN, PLASTIC, MICRO, BGA-71
文件頁數(shù)： 15/73頁
文件大?。?/td> 1928K
代理商： TPS65040ZQER
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
SLVS708B – NOVEMBER 2006 – REVISED APRIL 2007
Over recommended input conditions, T
A = –30°C to 85°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIAL INTERFACE TIMING(1)
CSPI (2)
tcymc
CCLK cycle time (3)
90
ns
twhmc
CCLK high level time
20
ns
twlmc
CCLK low level time
20
ns
tDS
CDATA setup time
20
ns
tDH
CDATA hold time
20
ns
tSD
CSTB input delay time
20
ns
twhms
CSTB high level time(3)
1.5
×tcycm
ns
tPSLH
CDATA transmission delay time (3)
CLOAD = 30 pF
26
ns
CSTB fall edge to CDATA rise edge
CDATA transmission delay time (3)
tPSHL
CLOAD = 30 pF
26
ns
CSTB fall edge to CDATA fall edge
tPLH
CDATA transmission delay time
CLOAD = 30 pF
26
ns
CCLK fall edge to CDATA rise edge
CDATA transmission delay time
CLOAD = 30 pF
ns
tPHL
26
CCLK fall ledge to CDATA fall edge
TSP(4)
tcw
TSPCLK cycle time(3)
76.9
ns
tcwh
TSPCLK high level time
15
ns
tcwl
TSPCLK low level time
15
ns
tsu
TSPDIN setup time
10
ns
th
TSPDIN delay time
10
ns
tcs
TSPEN setup time
10
ns
tch
TSPEN hold time
10
ns
trt
TSPEN rest time(3)
1
×tcw
ns
(1)
Internal logic is able to operate between 2.7 V and 3.1 V. But the buck boost DC/DC Converter, PAVREF and V11_V28TX should be
OFF. Also V12_V28RX, V13_V28A, V15_V18A, VGGE1_V28, VGGE2_V28 and VGGE3_V28 should be OFF or Low-power mode.
(2)
See Figure 88 to show the setup/hold time and pulse width on CSPI interface.
(3)
Not Production tested. Specified by using the reference EVM.
(4)
See Figure 90 to show the setup/hold time and pulse width on TSP interface.
22
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