
SLVSAU9A
– MAY 2011 – REVISED AUGUST 2011
Table 8. List of Recommended Inductors
SATURATION
CURRENT RATING
INDUCTANCE
DIMENSIONS
DC RESISTANCE
(30% inductance
TYPE
MANUFACTURER
[
H]
L x W x H [mm3]
[m
Ω typ]
drop, typ)
[A]
1.0
3.4
3.2 x 2.5 x 1.2
51
PST032251B-1R0MS-11
Cyntec
1.0
3.9
3.2 x 2.5 x 1.0
48
DFE322510C1276AS-H-
Toko
1R0N(1)
1.0
4.6
3.2 x 2.5 x 1.2
37
DFE322512C1277AS-H-
Toko
1R0N(1)
1.0
3.8
2.5 x 2.0 x 1.2
45
DFE252012C1239AS-H-
Toko
1R0N=P2
1.0
5.4
4 x 4 x 2.1
10
XFL4020-102ME1.0
Coilcraft
1.0
5.4
3.2 x 3 x 1.2
57
SPM3012T-1R0M
TDK
(1)
Release planned for Q4/2011. Contact manufacturer for details.
OUTPUT CAPACITOR SELECTION
The unique hysteretic control scheme allows the use of tiny ceramic capacitors. For best performance, ceramic
capacitors with low ESR values are recommended to achieve high conversion efficiency and low output voltage
ripple. For stable operation, X7R or X5R type capacitors are recommended.
The TPS6236x is designed to operate with an output capacitor of 10
F to 22F, placed at the device's output. In
addition a 0.1
F capacitor can be added to the output to reduce the high frequency content created by a very
sudden load change.
At light loads, if the device is operating in PFM Mode, choosing a higher value will minimize the voltage ripple
resulting in a better DC output accuracy.
Buffering the processor input by an additional ceramic capacitor in the range of 10
F to 22F improves the
voltage quality at the processor input and the dynamic load step behavior. This is especially true if the trace
between the TPS6236x and the microprocessor is longer than the smallest possible. This additional capacitor
needs to be taken into account for the recommended capacitance value. For stability, the sum of the VOUT
capacitors should not exceed 75
F effective capacitance.
Table 7 shows a list of tested capacitors. The TPS6236x is not designed for use with polymer, tantalum, or
electrolytic output capacitors.
OUTPUT FILTER DESIGN
The inductor and the output capacitor build the output filter. The load might be buffered with an input capacitor
CLOAD, which needs to be factored in. Based on the output capacitor and inductance recommendation sections
and factoring in CLOAD, these components should be in the range:
COUT + CLOAD= 10F to 75F
L = 1
H
For further performance or specific demands, these values might be tweaked. In any case, the loop stability
should be checked since the control loop stability might be affected.
THERMAL AND DEVICE LIFE TIME INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the
power-dissipation limits of a given component.
Thermal performance can be enhanced by proper PCB layout. Wide power traces come with the ability to sink
dissipated heat. This can be improved further on multi layer PCB designs with vias to different layers.
Proper PCB layout with focus on thermal performance results in a reduced junction-to-ambient thermal
resistance
θJA and thereby reduces the device junction temperature, TJ.
32
Copyright
2011, Texas Instruments Incorporated