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參數(shù)資料
| 型號： | TPS57114QRTERQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, 2000 kHz SWITCHING FREQ-MAX, PQCC16 |
| 封裝： | 3 X 3 MM, GREEN, PLASTIC, WQFN-16 |
| 文件頁數(shù)： | 18/37頁 |
| 文件大?。?/td> | 1309K |
| 代理商： | TPS57114QRTERQ1 |
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p
Iout m ax
p m od =
2
Vout
Cout
p
1
z m od =
2
Resr
Cout
C =
p mod
z mod
C
sw
=
p mod
2
gm
2 × c
Vo
Co
R3 =
Gm
Vref
VI
p
Ro
Co
C3 =
R3
SLVSAH5A
– DECEMBER 2010 – REVISED MARCH 2011
COMPENSATION
There are several industry techniques used to compensate DC/DC regulators. The method presented here is
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between
60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to
the TPS57114 -Q1. Since the slope compensation is ignored, the actual cross over frequency is usually lower
than the cross over frequency used in the calculations. Use SwitcherPro software for a more accurate design.
To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 36 and
Equation 37. For Cout, derating the capacitor is not needed as the 1.8 V output is a small percentage of the 10 V
capacitor rating. If the output is a high percentage of the capacitor rating, use the capacitor manufacturer
information to derate the capacitor value. Use Equation 38 and Equation 39 to estimate a starting point for the
crossover frequency, fc. For the example design, fpmod is 6.03 kHz and fzmod is 1210 kHz. Equation 38 is the
geometric mean of the modulator pole and the esr zero and Equation 39 is the mean of modulator pole and the
switching frequency. Equation 38 yields 85.3 kHz and Equation 39 gives 54.9 kHz. Use the lower value of
Equation 38 or Equation 39 as the approximate crossover frequency. For this example, fc is 56 kHz. Next, the
compensation components are calculated. A resistor in series with a capacitor is used to create a compensating
zero. A capacitor in parallel to these two components forms the compensating pole (if needed).
(36)
vertical spacer
(37)
vertical spacer
(38)
vertical spacer
(39)
vertical spacer
The compensation design takes the following steps:
1. Set up the anticipated cross-over frequency. Use Equation 40 to calculate the compensation network
’s
resistor value. In this example, the anticipated cross-over frequency (fc) is 56 kHz. The power stage gain
(gmps) is 25 A/V and the error amplifier gain (gmea) is 245 μA/V.
(40)
2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The compensation
network
’s capacitor can be calculated from Equation 41.
(41)
3. An additional pole can be added to attenuate high frequency noise. In this application, it is not necessary to
add it.
From the procedures above, the compensation network includes a 7.68 k
resistor and a 3300 pF capacitor.
Copyright
2010–2011, Texas Instruments Incorporated
25
Product Folder Link(s): TPS57114 -Q1
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