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參數(shù)資料
| 型號： | TPS54160DRCT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, 2500 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封裝： | PLASTIC, SON-10 |
| 文件頁數(shù)： | 45/50頁 |
| 文件大?。?/td> | 1375K |
| 代理商： | TPS54160DRCT |
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1
6
5
10
2
3
7
4
8
9
RT/CLK
BOOT
SS/TR
EN
VIN
PWRGD
PG
VSENSE
COMP
GND
DGQ PowerPAD PACKAGE
(Top View)
www.ti.com
SLVS795C – OCTOBER 2008 – REVISED OCTOBER 2010
DEVICE INFORMATION
PIN CONFIGURATION
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
BOOT
1
O
minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
COMP
8
O
components to this pin.
Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
EN
3
I
undervoltage lockout with two resistors.
GND
9
–
Ground
PH
10
I
The source of the internal high-side power MOSFET.
Thermal Pad
11
–
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or
PWRGD
6
O
EN shut down.
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
RT/CLK
5
I
a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is
re-enabled and the mode returns to a resistor set function.
Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the
SS/TR
4
I
voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
VIN
2
I
Input supply voltage, 3.5 V to 60 V.
VSENSE
7
I
Inverting node of the transconductance (gM) error amplifier.
Copyright 2008–2010, Texas Instruments Incorporated
5
Product Folder Link(s): TPS54160
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