參數(shù)資料
型號(hào)： TPS54140QDRCRQ1
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： SWITCHING REGULATOR, PDSO10
封裝： GREEN, PLASTIC, SON-10
文件頁(yè)數(shù)： 18/50頁(yè)
文件大?。?/td> 1602K
代理商： TPS54140QDRCRQ1
VSENSE
COMP
VO
R1
R3
C1
C2
R2
CO
RO
gmea
97 A/V
m
0.8V
PowerStage
gm
6 A/V
ps
PH
RESR
COUT
RL
b
a
c
VO
RESR
COUT
RL
VC
gmps
fp
fz
Adc
SLVSA24B
– OCTOBER 2009 – REVISED MARCH 2011
DETAILED DESCRIPTION (continued)
Figure 47. Small Signal Model for Loop Response
Simple Small Signal Model for Peak Current Mode Control
Figure 48 describes a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54140 power stage can be approximated to a voltage-controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 14 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node c in Figure 47) is the power stage
transconductance. The gmPS for the TPS54140 is 6A/V. The low-frequency gain of the power stage frequency
response is the product of the transconductance and the load resistance as shown in Equation 15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of
Figure 48. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same for the varying load conditions which makes it easier to design the frequency
compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on
the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number
frequency compensation components needed to stabilize the overall loop because the phase margin increases
from the ESR zero at the lower frequencies (see Equation 17).
Figure 48. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
Copyright
2009–2011, Texas Instruments Incorporated
25
Product Folder Link(s): TPS54140-Q1
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