參數(shù)資料
型號(hào)： TPS53353DQPT
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 穩(wěn)壓器
英文描述： SWITCHING REGULATOR, PDSO22
封裝： 5 X 6 MM, ROHS COMPLIANT, PLASTIC, SON-22
文件頁(yè)數(shù)： 9/25頁(yè)
文件大小： 556K
代理商： TPS53353DQPT
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IN
OUT
OUT LL
SW
IN
V
1
I
2
L
f
V
SLUSAK2
– AUGUST 2011
Ramp Signal
The TPS53353 adds a ramp signal to the 0.6-V reference in order to improve jitter performance. As described in
the previous section, the feedback voltage is compared with the reference information to keep the output voltage
in regulation. By adding a small ramp signal to the reference, the signal-to-noise ratio at the onset of a new
switching cycle is improved. Therefore the operation becomes less jittery and more stable. The ramp signal is
controlled to start with
–7 mV at the beginning of an on-cycle and becomes 0 mV at the end of an off-cycle in
steady state.
During skip mode operation, under discontinuous conduction mode (DCM), the switching frequency is lower than
the nominal frequency and the off-time is longer than the off-time in CCM. Because of the longer off-time, the
ramp signal extends after crossing 0 mV. However, it is clamped at 3 mV to minimize the DC offset.
Auto-Skip Eco-mode
Light Load Operation
While the MODE pin is pulled low via RMODE, TPS53353 automatically reduces the switching frequency at light
load conditions to maintain high efficiency. Detailed operation is described as follows. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that
its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The synchronous MOSFET is turned off when this zero inductor current is detected. As the
load current further decreases, the converter runs into discontinuous conduction mode (DCM). The on-time is
kept almost the same as it was in the continuous conduction mode so that it takes longer time to discharge the
output capacitor with smaller load current to the level of the reference voltage. The transition point to the
light-load operation IOUT(LL) (i.e., the threshold between continuous and discontinuous conduction mode) can be
calculated as shown in Equation 1.
where
SW is the PWM switching frequency
(1)
Switching frequency versus output current in the light load condition is a function of L, VIN and VOUT, but it
decreases almost proportionally to the output current from the IOUT(LL) given in Equation 1. For example, it is 60
kHz at IOUT(LL)/5 if the frequency setting is 300 kHz.
Adaptive Zero Crossing
The TPS53353 has an adaptive zero crossing circuit which performs optimization of the zero inductor current
detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and
compensates inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit. It
prevents SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too
early detection. As a result, better light load efficiency is delivered.
Forced Continuous Conduction Mode
When the MODE pin is tied to PGOOD through a resistor, the controller keeps continuous conduction mode
(CCM) in light load condition. In this mode, switching frequency is kept almost constant over the entire load
range which is suitable for applications need tight control of the switching frequency at a cost of lower efficiency.
Power-Good
The TPS53353 has power-good output that indicates high when switcher output is within the target. The
power-good function is activated after soft-start has finished. If the output voltage becomes within +10%
and
–5% of the target value, internal comparators detect power-good state and the power-good signal becomes
high after a 1-ms internal delay. If the output voltage goes outside of +15% or
–10% of the target value, the
power-good signal becomes low after two microsecond (2-
μs) internal delay. The power-good output is an open
drain output and must be pulled up externally.
The power-good MOSFET is powered through the VDD pin. VVDD must be >1 V in order to have a valid
power-good logic. It is recommended to pull PGOOD up to VREG (or a voltage divided from VREG) so that the
power-good logic is still valid even without VDD supply.
Copyright
2011, Texas Instruments Incorporated
17
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