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參數(shù)資料
| 型號： | TPS5210PWPR |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Voltage-Mode SMPS Controller |
| 中文描述： | 電壓模式開關(guān)電源控制器 |
| 文件頁數(shù)： | 26/29頁 |
| 文件大?。?/td> | 500K |
| 代理商： | TPS5210PWPR |
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TPS5210
PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
SLVS171A – SEPTEMBER 1998 – REVISED MAY 1999
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
layout guidelines
Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB design. The general design should proceed from the switching node to the output, then
back to the driver section, and, finally, place the low-level components. Below are several specific points to
consider beforelayout of a TPS5210 design begins.
1.
All sensitive analog components should be referenced to ANAGND. These include components connected
to SLOWST, DROOP, IOUT, OCP, VSENSE, VREFB, VHYST, BIAS, and LOHIB.
2.
Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors on V
O
, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
3.
Connections from the drivers to the gate of the power FETs, should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
4.
The bypass capacitor for the DRV regulator should be placed close to the TPS5210 and be connected to
DRVGND.
5.
The bypass capacitor for V
CC
should be placed close to the TPS5210 and be connected to DRVGND.
When configuring the high-side driver as a floating driver, the connection from BOOTLO to the power FETs
should be as short and as wide as possible. The other pins that also connect to the power FETs, LOHIB
and LOSENSE, should have a separate connection to the FETS since BOOTLO will have large peak
currents flowing through it.
6.
7.
When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from BOOT
to BOOTLO) should be placed close to the TPS5210.
8.
When configuring the high-side driver as a ground-referenced driver, BOOTLO should be connected to
DRVGND.
9.
The bulk storage capacitors across V
I
should be placed close to the power FETS. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
10. High-frequency bypass capacitors should be placed across the bulk storage capacitors on V
O
.
11. HISENSE and LOSENSE should be connected very close to the drain and source, respectively, of the
high-side FET. HISENSE and LOSENSE should be routed very close to each other to minimize
differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to
where HISENSE connects to Vin, to reduce high-frequency noise coupling on HISENSE.
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相關(guān)代理商/技術(shù)參數(shù) |
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| TPS5210PWPRG4 | 功能描述:DC/DC 開關(guān)控制器 Synch Buck Cntrlr Volume Control RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
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| TPS5211PWP | 功能描述:IC REG CTRLR BUCK PWM 28-HTSSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:4,000 系列:- PWM 型:電壓模式 輸出數(shù):1 頻率 - 最大:1.5MHz 占空比:66.7% 電源電壓:4.75 V ~ 5.25 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 85°C 封裝/外殼:40-VFQFN 裸露焊盤 包裝:帶卷 (TR) |
| TPS5211PWPR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| TPS524 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PHOTOVOLTAIC CELL FOR THERMOPILE DETECTION |
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