參數(shù)資料
型號: TPS51163DRCR
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, 660 kHz SWITCHING FREQ-MAX, PDSO10
封裝: 3 X 3 MM, GREEN, PLASTIC, SON-10
文件頁數(shù): 26/26頁
文件大?。?/td> 2137K
代理商: TPS51163DRCR
V
OUT
t – Time
t
SS_Delay
t
SS
PGOOD Delay at Startup
6% of V
OUT
1 V
PGOOD Delay
at Shutdown
V
COMP_EN
V
PGOOD
UDG-08108
www.ti.com ....................................................................................................................................................................................................... SLUS864 – MAY 2009
DETAILED DESCRIPTION
TPS51113 and TPS51163 are cost-optimized, single channel synchronous buck controllers that operate at a
300-kHz (TPS51113) and 600-kHz (TPS51163) fixed switching frequency, from a single 4.5-V to 13.2-V supply,
and supports output pre-biased startup. The overcurrent protection uses the low-side RDS(on) current sensing for
a low-cost, loss-less solution. Other features include input undervoltage lockout (UVLO), programmable
overcurrent threshold, soft-start, output oververvoltage/undervoltage (OV/UV) protection. The integrated gate
driver is powered directly by VDD. This makes the gate drive voltage more flexible.
SOFT START AND SELF-CALIBRATION
When VDD is above 4.3 V and the COMP_EN pin is released from being pulled low with open-drain system
logic, the controller enters the start-up sequence. There is a two stage start-up sequence for the COMP_EN
voltage. In the first phase of start-up (tSS_delay), the controller completes self-calibration and inhibits FET
switching, leaving both the upper and lower MOSFETs in the off state. In the second phase of start-up (tSS),
soft-start begins and switching is enabled. The internal reference gradually rises to 800 mV, and the output
voltage gets within its regulation point. The soft-start time (tSS) is internally programmed at 3.5 ms, and tSS_Delay is
programmed at 5.5 ms. On average, it takes approximately 9 ms for the output voltage to come into regulation
after the COMP_EN pin is released.
Figure 7 shows the typical startup and shutdown sequence. The overcurrent protection is enabled when the
soft-start begins and the soft-start voltage exceeds the pre-biased VOS voltage. The output overvoltage
protection is enabled approximately 64 clock cycles after the COMP pin voltage rises above 0.8 V (thereby
enabling the device). When the soft-start ends, the output undervoltage protection is enabled, and PGOOD
signal also goes high at the same time.
Figure 7. Typical Startup and Shutdown Sequence
Copyright 2009, Texas Instruments Incorporated
9
Product Folder Link(s) :TPS51113 TPS51163
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