參數(shù)資料
型號: TPS5110PWG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: 1.5 A SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, PDSO24
封裝: GREEN, PLASTIC, TSSOP-24
文件頁數(shù): 15/43頁
文件大?。?/td> 813K
代理商: TPS5110PWG4
TPS5110
SLVS025B APRIL 2002 REVISED JULY 2004
22
www.ti.com
APPLICATION INFORMATION
short circuit protection
The short circuit protection circuitry uses the UVP circuit to latch the MOSFET drivers. When the current-limit
circuit limits the output current, then the output voltage goes below the target-output voltage and UVP
comparator detects a fault condition as described above.
over voltage protection
The over-voltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the voltage
at either pin rises above 112% of the 0.85-V reference, the timer begins to charge the FLT capacitor. If the fault
condition persists beyond the time t(ovplatch), the fault latch is set and the high-side drivers are forced OFF, while
the low-side drivers are forced ON, and LDO regulator drivers are forced OFF.
CAUTION: Do not set the FLT pin to a lower voltage (or GND) while the device is timing out an OVP
or UVP event. If the FLT pin is manually set to a lower voltage during this time, output overshoot
may occur. The TPS5110 must be reset by grounding STBY and STBY_LDO, or dropping down
REG5V_IN.
disablement of the protection function
If it is necessary to inhibit the protection functions of the TPS5110 for troubleshooting or other purposes, the
OCP, OVP and UVP circuits may be disabled.
OCP(SBRC): Remove the current-limit resistors R13 to disable the current limit function.
OCP(LDO): Short-circuit R12 to disable the current limit function.
OVP, UVP: Grounding the FLT pin can disable OVP and UVP.
output capacitor selection for LDO
To keep stable operation of the LDO, capacitance of more than 33
F and RESR of more than 30 m are
recommended for the output capacitor.
power MOSFET selection for LDO
Also, to keep stable operation of the LDO, lower input capacitance is recommended for the external power
MOSFET. However, too small input capacitance may lead the feedback loop into unstable region. In such a
case, the gate resistor of several hundred ohms keeps the LDO operation in the stable state.
current protection for LDO
If excess output current flows through sense resistor (R12) and the voltage drop exceeds 50 mV, the output
voltage is reduced to approximately 22% of the nominal value, thus activates UVP to start the FLT latch timer.
When the set current is 4 A, the value of R12 is 12.5 m
.
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TPS5110PWRG4 功能描述:DC/DC 開關(guān)控制器 Sync Buck w/NMOS LDO Controller RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
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