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參數(shù)資料
| 型號： | TPS40055QPWPRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | PLASTIC, HTSSOP-16 |
| 文件頁數(shù)： | 2/28頁 |
| 文件大?。?/td> | 571K |
| 代理商： | TPS40055QPWPRQ1 |
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Clock
PWM RAMP
PowerGood
VIN
UVLO Threshold
1 2 3 4 5 6 7
1 2
TPS40054-Q1, TPS40055-Q1, TPS40057-Q1
SLAS482A – AUGUST 2005 – REVISED NOVEMBER 2005
APPLICATION INFORMATION (continued)
RT is the timing resistance in kW
The variable UVLO function uses a 3-bit full adder to prevent spurious shut-downs or turn-ons due to spikes or
fast line transients. When the adder reaches a total of seven counts in which the ramp duration is shorter than
the clock cycle a power-good signal is asserted and a soft-start initiated and the upper and lower MOSFETS are
turned off.
Once the soft-start is initiated, the UVLO circuit must see a total count of seven cycles in which the ramp
duration is longer than the clock cycle before an undervoltage condition is declared. (See Figure 5 ).
Figure 5. Undervoltage Lockout Operation
The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the
device at 10% below the nominal start up voltage, the maximum duty cycle is reduced approximately 10% at the
nominal start up voltage.
The impedance of the input voltage can cause the input voltage, at the controller, to sag when the converter
starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents
nuisance shutdowns at the UVLO point. With RT chosen to select the operating frequency and RKFF chosen to
select the start-up voltage, the approximate amount of hysteresis voltage is shown in Figure 6.
10
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