參數(shù)資料
型號(hào)： TPS40042DRCTG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, 700 kHz SWITCHING FREQ-MAX, PDSO10
封裝： 3 X 3 MM, GREEN, PLASTIC, SON-10
文件頁(yè)數(shù)： 13/35頁(yè)
文件大小： 746K
代理商： TPS40042DRCTG4
www.ti.com
Input Capacitor Selection (C1 & C2)
C
IN(min) +
I
LOAD
V
OUT
V
RIPPLE(cap)
V
IN
F
SW
(11)
ESR
MAX +
V
RIPPLE(ESR)
I
LOAD )
1
2
I
RIPPLE
(12)
I
RMS(cin) + IIN(rms) * IIN(avg) +
I
OUT
2
)
1
12
I
RIPPLE
2
V
OUT
V
IN
*
V
OUT
I
OUT
V
IN
(13)
MOSFET Switch Selection (Q1 & Q2)
P
G1SW +
1
2
V
IN
I
OUT
T
RISE ) TFALL
F
SW + VIN
I
OUT
Q
GS2_Q1 ) QGD_Q1
V
DD*VTH
R
DRIVE
F
SW
(14)
Q
GS2_Q1 ) QGD_Q1 t
P
G1SW
V
IN
I
OUT
V
DD * Vt
R
DRIVE
1
F
SW
(15)
P
CON_Q1 + D
I
OUT
2
)
1
12
I
RIPPLE
2
R
DS(on) +
V
OUT
V
IN
I
L(rms)
2
R
DS(on_Q1)
(16)
R
DS(on_Q1) +
P
CON_Q1
I
L(rms)
2
V
OUT
V
IN
(17)
SLUS777 – NOVEMBER 2007
Inductor Requirements
PARAMETER
SYMBOL
VALUE
UNITS
Inductance
L
0.8
H
RMS current (thermal rating)
IL(rms)
6.0
A
Peak current (saturation rating)
IL(peak)
7.08
A PG0083.801, 0.8
H is selected for its small size, low DCR and high current handling capability.
The input voltage ripple is divided between capacitance and ESR. For this design, VRIPPLE(CAP) = 50 mV and
VRIPPLE(ESR) = 25 mV. The minimum capacitance and maximum ESR are estimated by:
For this design, CIN > 60 F and ESR < 3.5 m. The RMS current in the input capacitors is estimated by:
With VIN = VIN(max), the input capacitors must support a ripple current of 1.56 ARMS. Two 1206, 100-F, X5R
ceramic capacitors with about 2-m
ESR and a 2-A RMS current rating are selected. It is important to check the
dc bias voltage derating curves to ensure the capacitors provide sufficient capacitance at the working voltage.
The switching losses for the upper switch MOSFET are estimated by:
For this design, switching losses are higher at low input voltage due to the lower gate drive current. Designing for
1 W of total losses in both MOSFETS and 20% of the total MOSFET losses in switching losses, we can estimate
our maximum gate-to-drain charge for the design at:
For a low-gate threshold MOSFET, and the TPS40042’s 5
and 3 drive resistances, we estimate a maximum
QGS2+QGD of 10.8 nC.
The conduction losses in the upper switch MOSFET are estimated by the RMS current through the MOSFET
times its RDS(on):
Estimating about 30% of total MOSFET losses to be high-side conduction losses, the maximum RDS(on) of the
high-side MOSFET can be estimated by:
For this design, with IL_RMS = 6 ARMS and 4.5 V to 0.9 V, RDS(on_Q1) is < 39 m for the upper switch MOSFET.
20
Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS40042
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