參數(shù)資料
型號： TPS3838L
廠商： Texas Instruments, Inc.
英文描述： NANPOWER SUPERVISORY CIRCUITS(處理器監(jiān)控電路)
中文描述： NANPOWER監(jiān)控電路（處理器監(jiān)控電路）
文件頁數(shù)： 6/11頁
文件大?。?/td> 173K
代理商： TPS3838L
TPS3836E18 / J25 / H30 / L30 / K33
TPS3837E18 / J25 / L30 / K33, TPS3838E18 / J25 / L30 / K33
NANOPOWER SUPERVISORY CIRCUITS
SLVS292A
–
JUNE 2000
–
REVISED JANUARY 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
RESET
(TPS3836)
VDD = 3.3 V,
VDD = 6 V,
VDD = 1.8 V,
VDD = 3.3 V,
VDD = 1.8 V,
VDD = 3.3 V,
VDD = 3.3 V,
VDD = 6 V,
VDD
≥
1.1 V,
IOH =
–
2 mA
IOH =
–
3 mA
IOH =
–
1 mA
IOL =
–
2 mA
IOL = 1 mA
IOL = 2 mA
IOL = 2 mA
IOL = 3 mA
IOL = 50
μ
A
VOH
High level output voltage
High-level output voltage
0.8
×
VDD
V
RESET
(TPS3837)
RESET
(TPS3836/8)
VOL
Low level output voltage
Low-level output voltage
0 4
0.4
V
RESET
(TPS3837)
Power up reset voltage
Power-up reset voltage
(see Note 2)
TPS3836/8
0.2
TPS3837
VDD
≥
1.1 V,
IOH =
–
50
μ
A
0.8
×
VDD
1.66
V
TPS383xE18
1.71
1.74
Negative-going input threshold
voltage (see Note 3)
h ld
TPS383xJ25
2.18
2.25
2.29
VIT
TPS383xH30
TA =
–
TA 40 C to 85 C
2.70
2.79
2.85
V
TPS383xL30
2.56
2.64
2.69
TPS383xK33
2.84
2.93
2.99
1.7 V < VIT <
2.5 V
2.5 V
<
VIT < 3.5 V
3.5 V < VIT
< 5 V
30
Vhys
Hysteresis at VDD input
Hysteresis at VDD in ut
40
mV
50
IIH
High-level input current
High level in ut current
MR
(see Note 4)
MR = 0.7
×
VDD,
VDD = 6 V
–
40
–
60
–
100
μ
A
CT
CT = VDD = 6 V
–
25
25
nA
IIL
Low-level input current
Low level in ut current
MR
(see Note 4)
MR = 0 V,
VDD = 6 V
–
130
–
200
–
340
μ
A
CT
CT = 0 V,
VDD = 6 V
VOH = VDD
VDD < 3 V
VDD > 3 V
–
25
25
nA
IOH
High-level output current
TPS3838
VDD = VIT + 0.2 V,
VDD > VIT,
VDD > VIT,
VDD < VIT
25
nA
220
400
nA
IDD
Supply current
250
450
10
15
μ
A
k
pF
Internal pullup resistor at MR
30
CI
NOTES:
Input capacitance at MR, CT
VI = 0 V to VDD
5
2. The lowest voltage at which RESET output becomes active. tr, VDD
≥
15
μ
s/V
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1
μ
F) should be placed near the supply terminal.
4. If manual reset is unused, MR should be connected to VDD to minimize current consumption.
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