參數(shù)資料
型號： TPS3707-33DGNRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封裝： GREEN, PLASTIC, MSOP-8
文件頁數(shù)： 22/23頁
文件大?。?/td> 775K
代理商： TPS3707-33DGNRG4
TPS3705xx
TPS3707xx
PROCESSOR SUPERVISORY CIRCUITS WITH POWERFAIL
SLVS184C NOVEMBER 1998 REVISED DECEMBER 2005
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements at RL = 1 M, CL = 50 pF, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
at VDD
VDD = VIT+ + 0.2 V,
VDD = VIT0.2 V
6
s
tw
Pulse width
at MR
VDD ≥ VIT++ 0.2 V,
VIL = 0.3 × VDD,
VIH = 0.7 × VDD
100
ns
tw
Pulse width
at WDI
VDD ≥ VIT++ 0.2 V,
VIL = 0.3 × VDD,
VIH = 0.7 × VDD
100
ns
switching characteristics at RL = 1 M, CL = 50 pF, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tt(out) Watchdog time out
VDD ≥ VIT+ + 0.2 V,
See timing diagram
1.1
1.6
2.3
s
td
Delay time
VDD > VIT+ + 0.2 V,
See timing diagram
140
200
280
ms
tPHL
Propagation (delay) time, high-to-low-level
output
MR to RESET delay
VDD ≥ VIT+ + 0.2 V,
VIL = 0.3 × VDD
50
250
ns
tPLH
Propagation (delay) time, low-to-high-level
output
MR to RESET delay
(TPS3707xx only)
DD
IT+
VIL = 0.3 × VDD
VIH = 0.7 × VDD
50
250
ns
tPHL
Propagation (delay) time, high-to-low-level
output
VDD to RESET delay
3
5
s
tPLH
Propagation (delay) time, low-to-high-level
output
VDD to RESET delay
(TPS3707-xx only)
3
5
s
tPHL
Propagation (delay) time, high-to-low-level
output
PFI to PFO delay
VDD = 2 V to 6 V
0.5
1
s
tPLH
Propagation (delay) time, low-to-high-level
output
PFI to PFO delay
VDD = 2 V to 6 V
0.5
1
s
相關(guān)PDF資料
PDF描述
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