參數(shù)資料
型號(hào)： TPS2848PWPR
廠商： Texas Instruments, Inc.
元件分類： MOSFETs
英文描述： 30V N-Channel PowerTrench MOSFET
中文描述： 30V的N溝道的PowerTrench MOSFET的
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 283K
代理商： TPS2848PWPR
SLVS367A
–
MARCH 2001
–
REVISED JUNE 2001
7
www.ti.com
electrical characteristics over recommended operating virtual junction temperature range,
V
CC
= 12 V, ENABLE = High, C
L
= 3.3 nF (unless otherwise noted) (continued)
dead-time control
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH(LOWDR)
VIL(LOWDR)
VIH(DT)
VIL(DT)
LOWDR high-level input voltage
Over full VDRV range
See Note 2
50
%VDRV
LOWDR low-level input voltage
Over full VDRV range
See Note 2
1
V
DT high-level input voltage
Over full VCC range
Over full VCC range
V(VDRV) = 4 V to 14 V
V(VDRV) = 4.5 V, TJ = 25
°
C, See Note 2
V(VDRV) = 14.5 V, TJ = 25
°
C, See Note 2
V(VDRV) = 4.5 V,
CL(Delay) = 50 pF
TJ = 25
°
C,
See Note 2
V(VDRV) = 14.5 V, CL(Delay) = 50 pF
TJ = 25
°
C,
See Note 2
V(VDRV) = 4.5 V,
CL(Delay) = 0 pF
TJ = 25
°
C,
See Note 2
V(VDRV) = 14.5 V, CL(Delay) = 0 pF
TJ = 25
°
C,
See Note 2
2
V
DT low-level input voltage
1
V
Deadtime delay
See Note 2
0.5
1
1.5
ns/pF
Dri er nono erlap time (DT to LOWDR)
Driver nonoverlap time (DT to LOWDR)
30
150
ns
30
100
ns
Driver nonoverlap time (LOWDR to
Driver nonoverla time (LOWDR to
HIGHDR)
75
180
ns
58
125
Driver nonoverlap time (LOWDR to
Driver nonoverla time (LOWDR to
HIGHDR)
50
125
ns
30
100
NOTE 2: Ensured by design, not production tested.
high-side driver
PARAMETER
TEST CONDITIONS
MIN
TYP
1.3
MAX
UNIT
–
V(BOOT) V(BOOTLO) = 4 V,
See Note 2
V(HIGHDR) = 0.5 V (src)
V(HIGHDR) = 4 V (sink)
V(HIGHDR) = 0.5 V (src)
V(HIGHDR) = 8 V (sink)
V(HIGHDR) = 0.5 V (src)
V(HIGHDR) = 14 V (sink)
V(HIGHDR) = 4 V (src)
V(HIGHDR) = 0.5 V (sink)
V(HIGHDR) = 7 V (src)
V(HIGHDR) = 0.5 V (sink)
V(HIGHDR) = 11 V (src)
V(HIGHDR) = 0.5 V (sink)
1
2
2.4
Peak output current
–
V(BOOT) V(BOOTLO) = 8 V,
See Note 2
2
2.4
A
2
3.3
–
V(BOOT) V(BOOTLO) = 14 V,
See Note 2
2
3.9
2
4.4
–
V(BOOT) V(BOOTLO) = 4.5 V
TJ = 25
°
C
45
6
ro
Output resistance
–
V(BOOT) V(BOOTLO) = 7.5 V,
TJ = 25
°
C
26
5
–
V(BOOT) V(BOOTLO) = 11.5 V,
TJ = 25
°
C
20
4
HIGHDRV-to-BOOTLO resistor
250
k
CL = 3.3 nF, V(BOOTLO) = GND,
TJ= 125
TJ = 125
°
C
3 3 F
V(BOOT)= 4 V
V(BOOT)= 8 V
V(BOOT)= 14 V
V(BOOT)= 4 V
V(BOOT)= 8 V
V(BOOT)= 14 V
V(BOOT) = 4 V
V(BOOT)= 8 V
V(BOOT)= 14 V
85
70
t /t
tr/tf
Rise and fall time
(see Notes 2 and 3)
65
ns
CL = 10 nF, V(BOOTLO) = GND,
TJ= 125
TJ = 125
°
C
10 F
170
140
100
Propagation delay time,
HIGHDR going low
(excluding deadtime)
V(BOOTLO) = GND, TJ = 125
C,
See Notes 2 and 3
°
120
tPHL
100
ns
80
NOTES:
2: Ensured by design, not production tested.
3. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the rDS(on) of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
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