參數(shù)資料
型號: TPS24701DGK
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: POWER SUPPLY SUPPORT CKT, PDSO8
封裝: GREEN, PLASTIC, MSOP-8
文件頁數(shù): 13/29頁
文件大?。?/td> 1956K
代理商: TPS24701DGK
T
FLT
T
10 A
C =
t
,
1.35 V
therefore,
10 A
C =
7 ms
52 nF
1.35 V
=
G009
1k
10
0.01
1
100
I
D
ra
in
-t
o
-So
u
rce
C
u
rre
n
t
A
D
S
0.1
0.01
0.1
10
100
1
Single Pulse
R
= 94C/W (min Cu)
θ
JA
1ms
10ms
100ms
1s
DC
Area Limited
by R
DS(on)
V
– Drain-to-Source Voltage – V
DS
2
ENTHRESH
VCC
1
2
R
V
R
=
+
SLVSAL3B
– MARCH 2011 – REVISED MAY 2011
CSD16403Q5 SOA curve at TJ = 25°C, the MOSFET can tolerate 12 A with 12 V across it for approximately 20
ms. If the junction temperature TJ is other than 25°C, then the pulse time should be scaled by a factor of
(150
°C – TJ) / (150°C – 25°C). Therefore, the fault timer should be set between 1.08 ms and 20 ms. For this
example, we will select 7 ms to allow for variation of system parameters such as temperature, load, component
tolerance, and input voltage. The timing capacitor is calculated in Equation 2 as 52 nF. Selecting the next-highest
standard value, 56 nF, yields a 7.56-ms fault time (see Equation 7).
(7)
Figure 31. CSD16403Q5 SOA Curve
STEP 4. Calculate the Retry-Mode Duty Ratio
In retry mode, the TPS24701 is on for one charging cycle and off for 16 charge/discharge cycles, as can be seen
in Figure 28. The first CT charging cycle is from 0 V to 1.35 V, which gives 7.56 ms. The first CT discharging
cycle is from 1.35 V to 0.35 V, which gives 5.6 ms. Therefore, the total time is 7.56 ms + 33
× 5.6 ms = 192.36
ms. As a result, the retry mode duty ratio is 7.56 ms/192.36 ms = 3.93%.
STEP 5. Select R1 and R2 for UV
Next, select the values of the UV resistors, R1 and R2, as shown in the application diagram on the front page.
From the TPS24700/1 electrical specifications, VENTHRESH = 1.35 V. The VUV is the undervoltage trip voltage,
which for this example equals 10.8 V.
(8)
Assume R1 is 130 k and use Equation 8 to solve for the R2 value of 18.7 k.
STEP 6. Choose RGATE, R4 and C1
In the application diagram on the front page, the gate resistor, RGATE, is intended to suppress high-frequency
oscillations. A resistor of 10
Ω serves for most applications, but if M1 has a CISS below 200 pF, then 33 Ω is
recommended. Applications with larger MOSFETs and very short wiring may not require RGATE. R4 is required
only if PGb is used; this resistor serves as a pullup for the open-drain output driver. The current sunk by PGb pin
should not exceed 2 mA. C1 is a bypass capacitor to help control transient voltages, unit emissions, and local
supply noise while in the disabled state. Where acceptable, a value in the range of 0.001
μF to 0.1 μF is
recommended.
ALTERNATIVE DESIGN EXAMPLE: GATE CAPACITOR (dV/dt) CONTROL IN INRUSH MODE
20
Copyright
2011, Texas Instruments Incorporated
Product Folder Link(s): TPS24700 TPS24701
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