參數(shù)資料
型號： TPS2359RHHT
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC36
封裝： 6 X 6 MM, GREEN, PLASTIC, QFN-36
文件頁數(shù)： 10/53頁
文件大?。?/td> 1074K
代理商： TPS2359RHHT
SLUS792F – FEBRUARY 2008 – REVISED AUGUST 2010
www.ti.com
Table 2. Summary of Registers (continued)
BIT
NAME
DEFAULT
DESCRIPTION
0
3BFT0
1
Setting bit increases 3B fault time by 0.5 ms.
1
3BFT1
0
Setting bit increases 3B fault time by 1 ms.
2
3BFT2
0
Setting bit increases 3B fault time by 2 ms.
3
3BFT3
0
Setting bit increases 3B fault time by 4 ms.
4
3BFT4
0
Setting bit increases 3B fault time by 8 ms.
5
3BEN
0
Clearing bit disables 3B.
6
3BUV
0
Setting bit prevents enabling unless OUT3B < bleed down threshold.
7
3BDS
0
Clearing bit disconnects OUT3B bleed down resistor.
Register 6 Read/Write system configuration
0
PPTEST
0
12-V pulldown test pin. Setting pin pulls the PASSx and BLKx pins to 0 V.
Clearing bit latchs off channels after over-current fault. Setting bit allows channels to
1
FLTMODE
0
automatically attempt restart after fault.
2
SPARE
0
This bit must always be set to 0.
3
3ORON
0
Setting bit enables 3A and 3B to prevent reverse current flow.
Non Redundant System in rush control bit. Setting bit allows increased inrush current
4
12VNRS
0
in 12A and 12B with proper setting of 12xCLx bits.
5
AIRM
0
Setting this masking bit prevents REG7 bits 3:0 from setting IRPT.
6
BIRM
0
Setting this masking bit prevents REG7 bits 7:4 from setting IRPT.
Setting bit allows the 12 V channels to operate despite loss of 3.3 V. This bit should
7
DCC
0
be low for uTCA and AMC applications
Register 7 Read only latched IRPT channel status indicators, cleared on read
0
12APG
0
Latches high when OUT12A goes from above VTH_PG to below VTH_PG.
1
12AFLT
0
Latches high when 12A fault timer has run out.
2
3APG
0
Latches high when OUT3A goes from above VTH_PG to below VTH_PG.
3
3AFLT
0
Latches high when 3A fault timer has run out.
4
12BPG
0
Latches high when OUT12B goes from above VTH_PG to below VTH_PG.
5
12BFLT
0
Latches high when 12B fault timer has run out.
6
3BPG
0
Latches high when OUT3B goes from above VTH_PG to below VTH_PG.
7
3BFLT
0
Latches high when 3B fault timer has run out.
Register 8 Read only latched overcurrent indicators, cleared on Read
0
12AOC
0
Latches high when 12A enters over-current.
1
12AFTR
0
Latches high if 12A fast trip threshold exceeded.
2
3AOC
0
Latches high when 3A enters over-current.
3
3AFTR
0
Latches high if 3A fast trip threshold exceeded.
4
12BOC
0
Latches high when 12B enters over-current.
5
12BFTR
0
Latches high if 12B fast trip threshold exceeded.
6
3BOC
0
Latches high when 3B enters over-current.
7
3BFTR
0
Latches high if 3B fast trip threshold exceeded.
Register 9 Read only unlatched FET status indicators
0
12ABS
-
High indicates BLKA commanded high.
1
12APS
-
Low indicates VPASSA > VOUT12A + 6 V.
2
3ABS
-
Low indicates IN3A > OUT3A.
3
12BBS
-
High indicates BLKB commanded high.
4
12BPS
-
Low indicates VPASSB > VOUTB + 6 V.
5
3BBS
-
Low indicates IN3B > OUT3B.
6
3AGS
-
Low indicates channel 3A gate is driven on ( VGATE > ( VIN + 1.75 V ).
7
3BGS
-
Low indicates channel 3B gate is driven on ( VGATE > ( VIN + 1.75 V ).
18
Copyright 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2359
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